Here is a great article about 2.5D and 3DIC technologies posted by Javier DeLaCruz, Manufacturing Director at eSilicon.
There are two general flavors of 3D-TSV technology. Images for these can be seen in the previous blog entry “The Future of ASICs in 3D.”
- 3D-IC has vias in silicon containing active circuitry.
- 2.5D is similar, but uses passive silicon, glass or organic interposers to enable very fine pitch interconnection between the active die mounted on top. There is some discussion about adding some basic active circuitry to these silicon carriers to enable better testability, but that is for a different blog entry. If glass or organic interposers are used, it is possible that this may not even include a TSV, but for simplicity in this entry we’ll just assume it does have TSVs.
There are also several combinations like rocky road that combine elements of each and introduce other ingredients. Much like consumers of ice cream that gravitate to certain flavors, so are the types of companies that will utilize each of these technology flavors, and for very good reasons.
Who will use 3D-IC?
ASIC 3D-IC implementations will be driven by several key market drivers. 3D-IC offers the promise of considerable miniaturization. The stacking of die that would otherwise be adjacent to each other reduces the area required on a PCB. While both 3D-IC and 2.5D technologies reduce PCB real estate, 3D-IC has the promise of having a greater real estate reduction. There is also the promise of lower power consumption when communicating with ASICs or ASSPs. Signals do not need to be driven at higher voltages since the IR drop from die vertically stacked is minimal, so the IO may just need to operate at the same voltage as the core of the die. In fact, the miniaturization must be coupled with lower power solutions or else these compact devices will overheat. Heat is a the biggest problem with 3D-IC, so this will likely be restricted to low-power devices, or solutions that can have inordiantely expensive heatsinking solutions, such as supercomputers.
There is also be a cost premium to this solution, as it would be less expensive to design these active die as a monolithic ASIC, or different MCM (multi-chip module) solution. The users for this will be those willing to pay a premium for this smaller, lower-power option. Hence, the main users for this will be mobile devices. A smaller phone with a longer battery life is worth more to the end consumer so the mobile component manufactures can justify this premium. The lower power usage in this space is also a great fit for this technology.
Full article here.