Home  >  ADVANCED PACKAGING  > The brave new world of modeling TSVs...
May 29th, 2012
The brave new world of modeling TSVs
With 2D ICs the prevailing notion has been that wire parasitics are relatively self-contained with the exception of very advanced designs running at hundreds of gigahertz. For the most part, the package designer and IC designer lived in their own separate worlds. With the advent of chip stacking using through silicon vias (TSVs), those worlds are being thrust together.
Send to a friend

As we start to stack chips they will interact from wire to wire on different chips, and the TSV is huge in comparison to the wires engineering teams are used to seeing. The TSV has significant resistance and capacitance effects, but it also has inductive effects that previously weren’t an issue other than with high frequencies. In 3D ICs the wires interact with each other and with the large vias—and it all has to be characterized.

Full text here.



Sep 17th
Sep 11th
Sep 11th
Sep 11th
Sep 11th
©2007 Yole Developpement All rights reserved                  Disclaimer | Legal notice | To advertise
Yole Développement: Le Quartz, 75 cours Emile Zola, 69100 Villeurbanne, France. TEL: (33) 472 83 01 80 FAX: (33) 472 83 01 83 E-Mail: info @yole.fr