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May 29th, 2012
 
The brave new world of modeling TSVs
 
With 2D ICs the prevailing notion has been that wire parasitics are relatively self-contained with the exception of very advanced designs running at hundreds of gigahertz. For the most part, the package designer and IC designer lived in their own separate worlds. With the advent of chip stacking using through silicon vias (TSVs), those worlds are being thrust together.
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As we start to stack chips they will interact from wire to wire on different chips, and the TSV is huge in comparison to the wires engineering teams are used to seeing. The TSV has significant resistance and capacitance effects, but it also has inductive effects that previously weren’t an issue other than with high frequencies. In 3D ICs the wires interact with each other and with the large vias—and it all has to be characterized.

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