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Jan 19th, 2012
 
The fast track to 3D-IC testing
 
Three-dimensional integrated circuit (3D-IC) systems offer the potential to deliver significant improvements in performance, power, functional density, and form factor over other packaging integration techniques. Despite substantial progress toward realizing 3D-IC systems, a variety of design, manufacturing, packaging, and testing issues still need to be addressed before cost-effective, high-volume production can be achieved. In this article we will focus on the test challenges and solutions, highlighting a design-for-3D-test architecture and implementation flow developed by researchers at Industrial Technology Research Institute (ITRI) based on the Synopsys test solution.
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Figure 1: 2.5D configuration with silicon interposer
Figure 1: 2.5D configuration with silicon interposer

2.5D before 3D
Advances in manufacturing and packaging technologies have already brought “2.5D” platforms within reach of early adopter design teams: 2.5D IC integration offers the potential to deliver a tighter form factor than standard systems-in-package by mounting multiple dies atop a common electrical interface, called a silicon interposer, and connecting them together with wires that run through the interposer [1]. The system I/Os are connected to the underlying package substrate using vertical Through Silicon Vias (TSVs), essentially cylindrical metal posts that extend partway through the interposer (Figure 1).

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