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Feb 20th, 2013
A reassessment of the use of Wide IO memory in smartphones
At the recent SEMI Europe 3D Summit Georg Kimmich of ST Ericsson gave an update on 3D integration for smartphones. It certainly was a sobering look at the use of wide IO memory and iMicronews thought it was worth: A Closer Look.
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It was exactly a year ago that we discussed the new JEDEC wide IO mobile DRAM standards and how they would be the driver for 3DIC commercialization [1]. Sophie Dumas of ST Ericsson Chair of the JEDEC committee reiterated the well accepted smartphone requirements for memory bandwidth and reported that the committee expected mass production by 2014.  

Expected mass production of wide IO DRAM [2]

At the recent SEMI Europe 3D summit Georg Kimmich of ST Ericsson gave a 2013 perspective of where things stand in the adoption of wide IO memory in smartphone devices. It appears that wide IO adoption has run into several unexpected obstacles such as:

Obstacles to the adoption of wide IO memory

As in all things 3D, the business model is required to be different and therefore is an obstacle.
It now appears that projected memory BW requirements for given GPU and CPU performances are  lower than initially expected do to improved memory hierarchy architectures and system cache strategies.
Memory options have also evolved to where LPDDR3 , a stacked PoP solution, offers the same bandwidth as wide IO at much lower cost and LPDDR4 will enable higher bandwidth than wide IO at similar power levels and at lower cost.  

Mobile device DRAM options

They have also found that thermal performance of wide IO is not on par with POP based LPDDR solutions. The 50-70um thick wide IO Si die with TSV inhibits lateral heat distribution. The thermally tightly coupled wide IO DRAM heats up much faster than in POP. The wide IO DRAM performance is reduced at Tj > 85C due to increased refresh cycle requirements and thus max performance peak is actually limited by the wide IO structure.

Comparison of wide IO and PoP thermal performance

Kimmich concludes that although 3D TSV technology appears ready for mass production, wide IO technology is not yet a fit for mainstream smartphones. LPDDR3 and LPDDR4 will be used in this application.
 He does offer the hope that, in the future “..3D smart partitioning options could allow higher performances, lower power, smaller form factors and faster time to market cycles – and due to increased cost/transistor on future silicon technology nodes…”

[1] P. Garrou, “Moving 3D IC forward with the standardization of wide IO DRAM”, 3D Packaging, issue no. 22, Feb 2012, p.24-25.
[2] S. Dumas, “LPDDR3 and Wide IO”, JEDEC Mobile Memory Forum, June 2011



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