Performance benefits:

This flexibility leads to the opportunity to obtain fine grain parallel operation that gives FPGAs their performance advantage. Additionally, the redundancy of FPGAs and memory devices enable defect mapping as an effective measure to deal with “known good die” challenges associated with using unpackaged (not fully tested) parts. The first SiCB design siXis is developing is depicted in figure 1. The SiCB is 48 mm X 80 mm and is .5 mm thick. Two bare die FPGAs, 22 mm X 17 mm, are bump bonded to the board. In addition, 16 memory die, 10 mm X 7 mm, are bump bonded to the board. Signal traces are 8 microns wide. The FPGA die are connected with 72 signal traces. Each memory chip is connected to an FPGA with 48 signal traces. The fine line widths available in silicon fabrication process allow us to route these signals (totaling approximately 1300) on the board using only two signal layers. The equivalent circuit we designed as a PCB implementation using packaged parts required 10 signal layers of 4 mil traces and large numbers of blind vias. This SiCB design is also used to realize a vertically integrated system

TSV’s feature large in the methods we use, which involves stacking SiCBs. At each end of the SiCB there are 5mm X 48 mm areas with arrays TSVs with a 200 micron pitch. SiCB to SiCB interconnection is accomplished using elastomeric connectors. These connectors are used widely in the semiconductor industry for testing of packaged BGA parts. These connectors are made of a pliant, rubber like material impregnated with a regular fine pitch array of conductors. Compressing the connector between two aligned SiCBs results in multiple conductors contacting backside pads surrounding the TSVs on each SiCB. These connections form a backplane in a set of stacked SiCBs. Using this method siXis is able to realize a backplane connection density of approximately 2000 I/Os per square cm, which would not be practical in a PCB design using conventional connectors. In addition to the signal layers outlined above, the SiCB design utilizes multiple power layers, see figure 5. These metal layers cover most of the SiCB. Vias between SiCB metal layers bring power and ground to the correct bumps on the FPGA and memory die. TSVs are used to bring power from backside of the SiCB to the topside power layers. Backside metal makes electrical contact with a power distribution structure that resides between the SiCBs.

Comparison of parasitics

Figure 1 show typical parasitic capacitance, resistance and inductance values for packaged parts on PCBs and bare die on SiCBs respectively. SiCB attached parts exhibit superior characteristics; the sum of the parasitic capacitances drop by about 8 to 1, the parasitic inductance drops by about 7 to 1, and the series resistance drops to a third. Our signal simulations comparing packaged and unpackaged FPGAs show that the unpackaged part has an output delay of about 300 ps vs. the packaged part delay of about 650ps. Since power dissipation from a signal is proportional to CV2 I/O power requirements drop to about 1/3 of the power needed for a packaged part.

By eliminating package parasitics we achieve a substantial reduction in I/O power as well as some improvement in I/O speed. In addition, we can achieve an additional power reduction and performance improvement because we use shorter lines with lower parasitics than an equivalent FR-4 based PCB. As SiCB technology matures and becomes widely used, we anticipate that IC designs will begin to appear in the marketplace with smaller lower power IO drivers.

Reliability benefits
There is virtually no temperature coefficient mismatch induced stress between a silicon circuit board and attached silicon die. In packaged devices, this stress leads to internal bump fractures and is the leading contribution to device failures. The absence of this stress means that no underfill is required to improve the reliability of the die to substrate bond. An important aspect of the SiCB is this inherently improved reliability as compared to an FR-4 substrate.

Daniel S. Stevenson is the VP of Technology Development at siXis, Inc. Daniel has over 30 years of experience in networking research and development including Bell Labs, Bell Northern Research, MCNC and RTI International. Daniel has been the principle investigator and project manager for numerous DoD sponsored collaborative research efforts with academia and industry. He was the founder and CTO of Celotek, a successful startup company that took information security research results he developed to the commercial marketplace. He has authored over 40 published papers and has given numerous conference presentations on research topics ranging from high performance distributed computing, network security and optical networking. Daniel has a BS in Physics from Stetson University and a MS in Physics from The University of North Carolina, Chapel Hill.


Robert O. Conn is the Chief Technology Officer at siXis, Inc. Bob has over 35 years of experience in semiconductor and systems engineering. He began his career designing integrated circuits at National Semiconductor in 1970 as a senior engineer. For 15 years, starting in 1981, he ran his own design consulting firm, Connsult, providing design and prototype work on more than 100 projects, and receiving national recognition. Conn spent 10 years at Xilinx and was a 2-time winner of the Ross Freemen award – Xilinx’s Innovator of the Year award. He holds more than 40 patents. He has a BSEE in electrical engineering from the University of California, Berkeley. Bob is lead architect for the SX1000 design and system.

About siXis

siXis is a spinoff from RTI International that aims to replace obsolete circuit board. Rather than conventional printed circuit boards made of fiberglass, siXis has developed an «All Silicon» Circuit Board (SICB) technology platform. siXis technology platform allows for the integration of semiconductor devices directly on a silicon substrate rather than a conventional printed circuit board substrate. Products that use SICB technology will exhibit higher performance and a smaller form factor, will be less expensive and will use less power than products available today. The company has recently raised $5 million. The funding for the company was led by Durham venture capital firm Intersouth Partners and RTI. The money will be used to develop the company’s first product and to expand its management team.