Physical Analysis of the Device

Step by Step Reconstruction of the Process Flow

Cost of Manufacturing and Estimation of Selling Price

Reverse Costing Analysis Report of the world record Fan-In Wafer Level Package realization featuring 309 pins at a pitch of 0.4mm!

Yole Développement is pleased to publish the reverse costing report of the latest Wafer Level Chipscale Package of Casio Micronics, the EWLP. It’s used in the Fujitsu MB39C311A, a Power Management Unit + Audio Interface Unit IC for mobile phone.

This EWLP is the last generation of WL-CSP. All the packaging operations are done at the wafer level. The ball pitch is only 0.4mm and only one redistribution layer is used for the 309 balls on 7.45x7.45mm package.

This WL-CSP with a pitch of 0.4mm is manufactured on 200mm wafers by Casio Micronics.

This report provides a complete teardown of the Casio Micronics 0.4mm pitch WL-CSP package including:

   • Detailed photos

   • Material analysis

   • Manufacturing Process Flow

   • In-depth economical analysis

   • Manufacturing cost breakdown

   • Selling price estimation