If we take a look at the amazing learning curve of the semiconductor industry in terms of chip density versus cost improvements over time, it is easy to realize that a gap is widening between the scaling evolutions of the chip front-end and the packaging-assembly manufacturing industries.

Wafer level packaging (WLP) is all about filling that gap: by making the packaging and assembly steps a whole collective wafer level process, packaging has now the potential to scale with the cost and size evolutions of most stringent semiconductor applications. As a generic description, WLP should be defined as “all packaging and assembly process steps are done at the wafer level, the last step being the chip dicing”. As a consequence of this, WLP does not require any intermediate substrate interposer: wafer level packaged components are directly “surface mountable” onto the circuit board. WLP is definitively a breakthrough packaging technology to be widespread even into the most cost sensitive applications as it will scale favorably with the trend to manufacture on ever increasing wafer diameters.

Actually, it is difficult to estimate what is the real status of volume production for WLP. This new packaging report aims at giving clues for understanding the technologies, trends and market status of WLP in Semiconductor ICs, CMOS imagers and MEMS applications.

Yole’s report gives a precise description of the different type of devices using WLP and their related manufacturing challenges. Examples of major market findings are:

• For CMOS imagers, WLP is indeed already an industrial reality. Today, about 35% of CMOS imagers to be found into latest consumer cell-phone and notebook cameras are encapsulated in a WL-CSP. We forecast that the technology could penetrate about 63% of this market as of 2012 as it will progressively widespread from CIF/VGAs to higher resolution image sensors.
• Semiconductors integrated circuits indeed represent the largest potential for WLP. It used to be mostly restricted to small I/Os applications such as integrated passive devices, LED drivers and amplifiers. However, WLP technology tends now to integrate higher I/Os devices (>50) and manufactured on ever larger wafer diameters (6”, 8” and 12”). Thus, we forecast WLP technology to grow from 1% of the mainstream IC with about 6 billions of units up to 2.5% by 2012. GaAs wireless RF chips are one of the most dynamic market segments with an expected CAGR > 100% over the 2007-2012 time period. Our analysis coers power, SAW, FBAR, logic, analog and memory devices as well.
• For MEMS, the term “WLP” has been extensively used in the industry since many years now. However, it is more a WLC “Wafer Level Capping” approach that is currently developed and not a real “true WLP”. Actually, production of first real WLP for MEMS started in 2006 and will account for a significant proportion of the WLP market by 2012 (see related figure 2). Companies like Samsung (KR), Dalsa Semiconductor (CA), Hymite (DK), Silex Microsystems (SW), Infineon (GE), IMT (US), TMT (TW) and VTI (FI) have all reported advanced developments in this area. Different types of MEMS going to WLP have been analyzed: inertial (gyroscopes, accelerometers), RF (switch & resonators), Si-microphones, Biochips and optical MEMS. Proportion of MEMS devices to be encapsulated in a real WLP is going to rapidly expand in volume with a CAGR above 100% over the 2007-1012 time periods.

Ultimately, WLP market value has been evaluated over 2007-2012 for MEMS, GaAs wireless, CMOS image sensors, power devices, SAW, FBAR, logic, memories and IPDs. Market forecasts have being established at the material, equipment and device levels, in both wspy (wafer start per year) and in MUS$

Yole’s “WLP & Embedded Dies Technologies” new report covers the manufacturing challenges faced for the wafer level packaging of MEMS, CMOS image sensors and Semiconductor ICs. Technology issues are presented and discussed in details such as encapsulation processes (wafer bonding, thin film), lithography (stepper vs. mask aligners), materials associated (dry films, liquid, negative and positive photoresists), deposition methods (Spin, Spray coating, EDPr plating on high topographies…), non-lithographic processes (such as ECPR), Bumping technologies (Ball loading, electroplating copper pillars, solder, gold microbumps, screen printing techniques, C4NP), passivation layers for the UBM, RDL and TSV process steps (based on polyimide, BCB, PBO, SU8…).

It also covers in a separate chapter a presentation of the different technologies and integration requirements for embedded dies at the substrate level. This is a relatively new 3D approach developed by the PWG industry in order to meet the integration requirement of next System in Package (SiP) module configurations.

Company activities listed in the report:

Amkor, Asahi, ASE, Analog Devices, Air Products, Austriamicrosystems, Arch Chemical, AvagoTech, AVX, Brewer Sciences, Bosch, California Micro Devices, Casio Computer, CEA Leti, Clover Electronics, Dalsa Semiconductor, DNP, DOW Chemical, Dupont, Enthone, Epcos, EPWorks, EVGroup, Fraunhofer-IZM, Freescale, Fujikura, Fujifilm, Hymite, i2a, Imbera Electronics, Ibiden, IBM, IME, IMEC, IMT, Infineon, JSR Micro, Mentor Graphics, MicroChem, Micron, National Semiconductor, Nanya, NEC Toppan Circuit, Nokia, Philips-NXP, OKI Electric, Omnivision, OptoPAC, Pac Tech, Replisaurus Technologies, RFMD, Rohm & Hass, Samsung, Schott, Sensonor, Silex, SiTime, Shin-Etsu, Shinko, Skyworks, StatsChipPac, STMicroelectronics, SPIL, Sumitomo, SUSS MicroTec, Telephus, Tessera, Texas Instruments, TOK, Toshiba, Triquint, Tronic’s Microsystems, Touch Microsystems Technology, TSMC, Ultratech, VTI, Xintec, ZyCube

In this report you will find the following:

• WLP Definition & Market drivers
• Key technologies for WLP manufacturing
• Photo Resists & Dry films for WLP
• Lithography options for WLP
• Materials selection for Wafer level packaging applications
• WLP Market forecasts 2007- 2012 at the device level
• WLP Materials & Equipments Market forecasts 2007 – 2012
• WLP manufacturing challenges per applications: MEMS, CMOS image sensors and ICs
• WLP infrastructure & Supply Chain evolution
• Embedded Die Technologies & Players

Benefits of the report

Benefits of the report for equipment and material manufacturers:

• Analysis of the structure of WLP & Embedded Components industry and its evolution
• Description of the key manufacturing process steps and their related challenges
• Calculation of wafer volumes to be produced including diameter evolution forecast for each market segments
• Link to equipment and material market forecasts breakdown

Benefits of the report for the devices manufacturers and others:

• Analysis of current applications and potentials for future businesses (from MEMS, CMOS image sensor to Semiconductor IC applications)
• Competitive analysis (from large companies, research / IP structures to small start-ups)
• Volumes and forecasts breakdown per application in MUS$ from 2007 to 2012

• List of main figures & tables ………………………………...… 5
• Objectives of the report ………………………………………..…. 6
• Executive Summary ………….……....….….................................. 7
  • WLP Market Forecasts in for CIS, MEMS and ICs ............ 8
  • WLP detailed forecasts: Product Breakdown .................. 10
  • WLP Market Segments Attractiveness …..………………... 12
  • Scope of the Study & Definitions …..………………………. 14
  • 3D interconnects Technology Roadmap …..……..….…….. 16
  • WL-CSP Applications Space …..……………………............. 17
• WLP Definition & Market drivers …………………………. 21
  • History & definitions ………………….…………..................... 22
  • Wafer Level vs. Traditional Packaging supply chain …...... 24
  • Market drivers for WLP ………………………………………… 29
  • Flip-chip vs. WLP bumps characteristics …………………… 32
  • Flip Chip, BGA & WLP technologies comparison ............. 34
• Key technologies for WLP manufacturing ……….… 36
  • Key process steps, technologies and equipments .......... 37
  • Redistribution process details ........................................... 39
  • Future options for redistribution technologies ................ 43
  • WLP trends at the RDL level .............................................. 44
  • High reliability WLP without underfiller ........................... 45
  • Fujikura and Infineon compliant bumps .......................... 46
  • Integration of passives at the RDL level ........................... 48
  • Example of integration of IPDs at the RDL level .............. 50
  • Reliability & Tests issues for WLP ............................…….51
• Photo Resists & Dry films for WLP ………………………....… 52
  • Passivation & RDL Resists & Films specifications ................ 54
  • Bumping applications Resists & Films specifications ........... 55
  • Thick photoresists applications ........…………………………….56
  • Permanent vs. strippable resists .............................................. 59
  • Positive vs. negative photo-resists .........………………………..60
  • SU8 epoxies for packaging applications …………………......... 62
  • Dry films for WLP ........................................................................ 66
  • Material Segmentation per WLP applications ......................... .67
  • Bumping technologies overview ............................................... 68
  • Lead Free Plating Process ......................................................... 71
  • Typical Solder bump process flow …………………….……....... 72
  • A specific bumping approach: C4NP ........................................ 73
  • Example of application: Gold bumps for LCD driver ICs ........ 77
• Lithography technologies for WLP ………………………….... 79
  • Deposition technologies comparison ...................................... 80
  • Spin / Spray coating / Lamination / EDPr .................. 81
  • Stepper vs. Mask aligner for WLP ............................................. 83
  • Cost of ownership comparison .................................. 87
  • Non-Lithographic plating (ECPR) for IPD & RDL ..................... 89
  • Conclusions on Materials for Advanced Packaging …. 90
  • Materials selection summary for Advanced Packaging ... 91
  • Material challenges summary ………………………………. 92
  • Dry film vs Liquid Resists? ................................................ 93
  • Materials critical Properties for WLP ……………………… 95
  • Electronic material suppliers offer .................................... 96
  • WLP Market forecasts 2007- 2012 ………………………. 99
• WLP Market forecasts in M$ for CIS, MEMS and ICs ........ 100
  • WLP Market forecasts in wspy for CIS, MEMS and ICs ... .101
  • WLP detailed forecasts: Breakdown by product in wspy . 102
    • Details for GaAs Wireless / IPDs / memories / Power / SAW / FBAR / Logic / Analog / CMOS image sensors / Inertial – RF – Microphone & Optical MEMS
  • WLP detailed forecasts: Breakdown by product in M$ ... 103
    • Details for GaAs Wireless / IPDs / memories / Power / SAW / FBAR / Logic / Analog / CMOS image sensors / Inertial – RF – Microphone & Optical MEMS
  • WLP Market Segments Attractiveness (CAGR, M$) …….. 104
  • WL-CSP penetration rate into Nokia’s cell-phones .......... 105
• WLP Materials & Equipments Market forecasts .............. 106
• Semiconductor Equipment forecasts by segment …….... 108
• WLP Equipment forecasts in MUS$ .................................. 109
• Packaging Materials Market 2007 status ………………….. 110
• Materials overview used for WLP ...................................... 111
• WLP Materials Market forecasts Breakdown ………………112
  • Details for UBM / RDL / Dielectric passivation / Wafer level bonding / encapsulation / i-line / black resists
• Permanent vs. Strippable WLP resists forecasts ............ 113
• WLP Applications ……………………………………………………..… 114
  • WLP for IC Semiconductors ………..………….………………. 116
    • WLP IC wafer forecasts ………………….…………………... 117
    • Detailed breakdown ............................................................ 118
      • Details for IPDs / Memories / Logic / Analog / GaAs Wireless / FBAR / SAW / Power components
    • WLP penetration rate % into mainstream Semiconductor 124
    • WLP drivers for IC applications ........................................ 125
    • WLP case for DR memories ......................................... 126
    • WLP Technical & Cost Challenges Summary .................. 129
    • Example of WLP IC player integrations ............................. 131
      • Details for Infineon / Fraunhofer IZM / STM / Epcos / AvagoTech / Triquint / RFMD / Skyworks
  • WLP for CMOS image sensors ............................................... 141
    • WLP for CIS market forecasts (in wspy) ………………….. 142
    • WL-CSP Market forecasts (M$) for CIS per resolution …. 143
    • CIS suppliers Market Shares (Q1 2007) ... ………………….144
    • WL-CSP CIS in a downstream product ............................ 145
    • Market drivers for WL-CSP in CIS ..................................... 146
    • Future challenges at the wafer level for CIS ... ……………147
    • Wafer level optics ……………………………………………….149
    • ‘‘Camera Cube’’ CMOS imagers manufacturing steps ..... 150
    • NanoSpray technology for Dielectric deposition in TSV .. 153
    • Development illustrations: Omnivision / Toshiba /OKI / STMicroelectronics / EPWorks / OptoPAC ......................... 154
  • WLP for MEMS ............................................................................ 162
    • MEMS packaging: Different approaches for WLP ……….... 163
    • MEMS overall Market per application (M$) .......................... 165
    • WLC MEMS wafers forecasts in wpy and in M$ ................. 166
    • WLP MEMS wafers forecasts per application in wpy / M$ .. 168
    • MEMS packaging Trends: Roadmap of Analog Devices ... 170
    • Wafer Level Capping (WLC) techniques ............................. 171
      • Application examples / Wafer level bonding / Thin film encapsulation / materials involved
    • Wafer Level Packaging (WLP) techniques: ......................... 186
      • Status / Technologies / Examples of integrations
• WLP infrastructure & Supply Chain ……………………… 204
  • WLP activities: Worldwide geographical mapping .............. 205
  • WLP infrastructure challenges .............................................. 206
  • WLP supply chain ................................................................... 207
  • Back-end players packaging activities breakdown ............. 210
  • Top packaging and testing houses market shares ............. 211
• Embedded Die Technologies …………………………….…. 213
  • Embedded module technology roadmap ............................. 214
  • Embedded Passives with 3D Packaging ............................. 215
  • Embedded packaging technologies vision from ST ........... 216
  • Passives integration options ................................................. 217
  • Freescale: 3D integration vision ............................................ 218
  • Imbera embedded die technologies ...................................... 219
  • Embedded dice technology from ST ..................................... 221
  • Nokia Embedded Technologies Packaging Roadmap ......... 222
  • Embedded active device by NEC Toppan Circuit Solutions 223
  • Memory + CPU package architecture options ...................... 224
  • Summary of on-package embedded architectures .............. 225
  • Intel’s Package Architecture Roadmap for 3D integration …226
  • Embedded technologies: Player’s Activities Comparison …227
  • Conclusions on Embedded Die Technologies ……………… 228
• Main conclusions …………………………………………………….. 229
• Annexes ……………………………………………………………………. 231
  • Yole’s 3DIC / TSV / WLP activity presentation ...................... 232
  • Yole Development Company presentation ........................... 233

LIST OF FIGURES:

• WLP Market Forecasts in for CIS, MEMS and ICs …………............ 8
• WLP detailed forecasts: Product Breakdown ............................... 10
• WLP Market Segments Attractiveness …..………………............... 12
• 3D interconnects Technology Roadmap …..……..….…….……….. 16
• WL-CSP Applications Space …..……………………........................ 17
• Material Segmentation per WLP applications ................................ 67
• Bumping technologies overview ..................................................... 68
• Steppers vs. Mask aligners for WLP: COO comparison ............... 87
• Material challenges summary …………………………………………. 92
• Materials critical Properties for WLP ………………………………… 95
• Electronic material suppliers offer .................................... ……..… 96
• WLP Market forecasts in M$ for CIS, MEMS and ICs ................... 100
• WLP Market forecasts in wspy for CIS, MEMS and ICs ............... 101
• WLP detailed forecasts: Breakdown by product in wspy ………. 102
  • Details for IPDs / memories / Power / GaAs Wireless / SAW / FBAR / Logic / Analog / CMOS image sensors / Inertial – RF – Microphone & Optical MEMS for 2007-2012
• WLP detailed forecasts: Breakdown by product in M$ .............. 103
  • Details for IPDs / memories / Power / GaAs Wireless / SAW / FBAR / Logic / Analog / CMOS image sensors / Inertial – RF MEMS – Microphone & Optical MEMS for 2007 - 2012
• WLP Market Segments Attractiveness (CAGR, M$) ………….…... 104
• WLP Equipment forecasts in MUS$ ............................................... 109
• Packaging Materials Market 2007 status ………………………….. 110
• WLP Materials Market forecasts Breakdown ..…………………… 112
  • Details for UBM / RDL / Dielectric passivation / Wafer level bonding / encapsulation / i-line / black resists for 2007-2012
• Permanent vs. Strippable WLP resists forecasts ........................ 113
• WLP IC wafer forecasts ………………….………………….............. 117
• Detailed breakdown ........................................................................ 118
  • Details for IPDs / Memories / Logic / Analog / GaAs Wireless / FBAR / SAW / Power components for 2007 -2012
  • Details for Dry films, BCB, SU8, Polyimide, PBO and black resists WLP penetration rate % into mainstream Semiconductor …….. 124
• WLP for CIS market forecasts (in wspy) per resolution …..…... 142
• WL-CSP Market value forecasts for CIS per resolution ……….. 143
• CIS suppliers Market Shares Q1-2007 ......………………………… 144
• MEMS overall Market per application (M$) .......................... ……. 163
• WLC MEMS wafers forecasts in wspy / M$ …………................... 164
• WLP MEMS wafers forecasts per application in wspy / M$ ….... 166
• WLP activities: Worldwide geographical mapping ...................... 203
• WLP infrastructure challenges ...................................................... 204
• Back-end players packaging activities breakdown ..................... 208
• Top packaging and testing houses market shares .................... 209
• Nokia Embedded Technologies Packaging Roadmap ................ 220
• Embedded technologies: Player’s Activities Comparison …….. 222