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Fan-Out Wafer Level Packaging is now entering a new era: with a high expected growth of the market, multiple new companies, OSATs and even foundries, are attracted and involved in this platform. According to Yole Développement’s "Fan-Out and Embedded Die: Technologies & Market Trends report”, the market reached more than $150M in 2014 and a CAGR of 30% for the next 5 years is expected, driven by mobile applications and the need of very thin packages for high I/O devices.

FOWLP activity revenus Fan Out and Embedded Die Yole Développement 2015

(Fan-Out and Embedded Die: Technologies & Market Trends report, Yole Développement, February 2015)


Yole Développement recently had the opportunity to interview David Butler, VP of Product Management and Marketing at SPTS division within Orbotech. David has shared his point of view on fan-out wafer level packaging platform with us, as follows:

Yole Développement:
Fan-Out, as an emerging packaging platform has certainly raised a lot of interest in the industry. Investments in equipment and other necessary infrastructure to support fan-out technology have been made and fan-out has already been successfully adopted in production. We continue to see a high interest in this platform and we are expecting a high growth for the next few years, therefore, further equipment needs and investments. Can you please confirm and comment on the industry’s preparation for the next wave of growth in fan-out? Have you seen increasing equipment spending in the past year, and do you believe it will continue to further increase this year as well?

David Butler: In the last 12 months, FOWLP has emerged from a relatively small base to become one of the most active topics in the packaging world. It started with eWLB, the Infineon designed platform that was licensed to a few companies at the end of the last decade, notably STATS ChipPAC and NANIUM. Those two companies now lead the FOWLP market. During 2014, a number of companies announced their own FOWLP platforms including Amkor with SLIM, SPIL SLIT, Intel EMIB and perhaps the most vocal, TSMC with InFO. We know of more companies who have plans in that direction but have not yet gone public. These new announcements have coincided with a ramp in equipment spend, and SPTS have benefitted from that. One major OSAT told me that of all their projects that come under the heading of “Advanced Packaging”, their FOWLP project had received by far the most interest from their customers, backed up with considerable urgency. The need is real and immediate.

YD: What are the main applications, devices that will drive this next growth?

Are mobiles and tablets for high bandwidth applications. Baseband processors, RF transceivers and power management IC’s are being embedded in these mold wafers. NANIUM speak of the advantages of being able to mount RF devices in close proximity to multiple passives, delivering data transfers >60GHz. Line and space reductions will move FOWLP into the reach of even higher performance parts such as memory and application processors.

YD: We have heard about TSV adoption for high-end applications, however, still struggling when it comes to consumer applications, especially for memories, where cost is very critical. Is fan-out a lower cost alternative addressing this market segment where 3DIC platform is still being delayed?

Yes it is. While stacked memory containing TSV’s is finally going into production, it will serve the very high performance end of the market such high bandwidth GPU applications. In these markets, the committed gamer will not be worried by a price premium. However, for the consumer market, TSV’s are still too expensive; I’ve seen numbers suggesting anywhere from 3 to 5x more costly than the $0.01 per cm2 proposed by Qualcomm. FOWLP will take some segments of the market previously expected to be satisfied by Si interposers.

YD: Can fan-out provide the same performance that TSVs can at lower cost or the industry has no other choice than to accept fan-out until 3DIC will be ready? Do you see 3DIC and fan-out to be competing technologies? Do you think 3D stacking using TSVs, once adopted in production, will be replacing fan-out, especially for the applications driven by need of higher performance, or fan-out will be rather competing more with the traditional packaging technologies, such as WLCSP, FCBGA, Wire bonded packages?

: For some devices, fan-out will match the performance of 2.5D at lower cost and therefore will become the packaging method of choice. As always in the industry, the lowest cost technology will be used until the market demands cannot be achieved. 3D TSV will be used for the high bandwidth packages coming out now; the AMD GPU with HBM, Intel’s Knights Landing… I don’t see these switching to FOWLP anytime soon.

Looking at current activity, I see the market splitting into three fundamental segments; 3DIC for high performance, where cost considerations are secondary; FOWLP for high density applications, where cost matters; and finally wire bonding which is not going to disappear. There will be areas of overlap of course. The relative success of 3DIC vs FOWLP will partly depend on who gets into high volume first.

YD: From equipment perspective, most of the high-volume production today is done using 300mm wafer processing infrastructure, however, the industry, is aggressively developing, in parallel, in order to further reduce cost, a panel based infrastructure. Is the supply chain ready to support panel manufacturing or will it first move into 330mm and then panel manufacturing?

All the OSATs have panel programs because of the obvious cost benefits, but my sense is that the momentum is slowing. I think the infrastructure is lacking, the equipment market size for substrates that can take 1000’s of devices is not compelling for equipment makers. Managing warpage over a large area is not a trivial task, and I don’t see panel technology catching the line/space dimensions available on wafer formats. I see panels as a low density substrate, much as it is now.

YD: Can you comment on the timing for 330mm adoption as well as panel adoption? 330mm transition is a result of panel manufacturing un-readiness? If yes, what are the remaining challenges to be addressed before industry can switch to panel manufacturing? Is Orbotech prepared to support both these 2 transitions? Once the industry will move to panel, what will happen with the existing 300mm infrastructure utilized for fan-out? Will both wafer and panel infrastructure coexist or, will it be difficult for those already invested in 300mm to compete with the new players coming in with panel infrastructure?

330mm is in production now. Time will tell if it will become mainstream compared to 300mm, as it does require new investment which is always a challenge. If the 330mm makers become dominant, then those on smaller substrates will have to match or sell at smaller margins.

In Orbotech, we have two parts to our business which take a different stance; the wafer processing part in the UK is focused on high density solutions where business models can support higher end equipment. We do not believe that panel processing will reach sub 5/5 line & space, so have no plans to make panel equipment. In contrast, the Israeli operation makes optical inspection and laser drilling equipment for the PCB and flat panel markets, and will certainly play a role as panel makers push line widths below 30um.

To answer your last question. If panels do reach the fine line & space required for high density, then those on wafer sized formats will lose share. But as I said, I see panels playing in the low density markets only.

YD: What are the requirements and challenges coming from Fan-Out manufacturers regarding equipment, in terms of warpage, cost, precision? What are the critical steps in the process? How is SPTS handling these demands and what is your roadmap?

Warpage is a big challenge. The epoxy mold wafers can be warped after curing, and the size and shape of the warpage can change for different shapes and density of the embedded die. In an effort to reduce cost and package height, the thickness of the substrate reduces too, although this tends to make the wafer less stiff and therefore flatten under gravity. We have spent a lot of resource on developing hardware that can handle wafers up to 6 mm bow, and processes that minimize temperature induced shape shift. I do not expect the industry to move to much more than 6mm bow, since it is not simple to make uniformly thick conductors on a substrate showing that amount of warpage.

Another challenge is contamination. The mold contains moisture and other solvents which will contaminate the metal pad unless managed correctly. As an added complication, these wafers cannot tolerate high temperatures, so the PVD equipment supplier cannot do a simple 400°C degas as he would in the front-end of the fab. The chart below shows the effect of degas time on contact resistance; it can take up to 35 mins to get a clean metal-to-metal contact when embedded in epoxy mold. In practical terms, if you use a single wafer degas on your PVD system, you will be facing a throughput much less than 5wph, and that will not satisfy this market.

When we first started running eWLB wafers 7 years ago, we quickly realized that a new degas method was needed, and we developed a Multi-Wafer Degas, MWD. This holds up to 75 vertically stacked wafers at high vacuum, connected directly to the high vacuum side of the PVD system. With the MWD, each individual wafer can spend up to 1 hour degassing at low temperatures, but because it happens in parallel, there is always a “dry” wafer ready for process.

Sigma fxP PVD with integrated MWD SPTS Orbotech FanOut Yole Développement 2015YD: STATS ChipPAC and NANIUM are the main players today when it comes to fan-out high volume production, however, strong players such as ASE, SPIL, and especially TSMC are entering this field. How do you see the future in fan-out? Who do you envision will be taking the lead in the next 5 years? Do you think STATS ChipPAC will be able to maintain its leadership, taking into consideration both their acquisition as well as fast rising and strong competition?

It’s a fast moving market, and STATS ChipPAC and NANIUM have a lead that they have built up over 5 years. We’ve seen a number of others enter in recent months, partly under pressure from big fabless companies who have become discouraged by the cost of TSV. In addition to the ones in your question you can add Intel, Amkor plus others who have yet to go public.

Who will win? The first question is which approach will win – eWLB is no longer the only FOWLP platform, although it certainly leads on maturity. One interesting approach is the so called RDL first, where the interconnect is formed on a Si wafer in a foundry. Die are placed on top of the interconnect and then mold is spun to embed them. The final step is to remove the foundry Si substrate by grind & etch. In theory, this offers the highest density interconnect of all FOWLP approaches, because the minimum line & space is straight from the front-end. Cost and warpage are the unknown factors.

TSMC have made a lot of noise with InFO, and their lithography capability is far in advance of the OSATs. But they work to different business models, and an OSAT will always be able to accept lower margins.

I hesitate to say who will lead in 5 years. I suspect it will play out to two names: one who wins the volume, and one who has the best technology – that will not necessarily be the same company.

YD: SPTS has recently been acquired by Orbotech. Can you comment how it has impacted SPTS and how is Orbotech now positioned to address the Advanced Packaging market?

We were acquired in Aug 2014. Orbotech saw that their PCB business in particular had become a slow growth market and increasingly commoditized. They also saw a threat coming from higher up the food chain, where new formats such as interposers and FOWLP could start to take share from the PCB specialists. During their strategic planning process about 18 months ago, they set plans in motion to accomplish several objectives: they wanted to move further up the value chain in electronics manufacturing, and to do a transformational/strategic acquisition that would add $150M to $200M to the company’s top line. As a result, Orbotech decided they needed to take a position in advanced packaging, or the so-called Middle End of Line (MEOL), and looked to do it in several ways; look for expanding market channels for their existing products, focus their existing products and technologies onto wafer format and acquire an MEOL equipment specialist. SPTS was an excellent fit to accomplish those objectives.

The impact on SPTS’s business has been 100% positive. Firstly, I can now go into a tier 1 customer as part of a $750M to $1Bn company, which instantly removes the potential barrier of size that can impede a smaller supplier. We now have more solutions to offer a customer, for instance laser drilling for FOWLP mold wafers to complement the PVD, etch and CVD equipment out of SPTS. Further, there are aspects of each other’s technology that could add value to our respective offerings, for instance for SPTS, in the fields of endpointing or direct patterning. As a result of the acquisition, the new Orbotech becomes a substantial supplier to packaging manufacturers working in MEOL to BEOL, with the resources to support and develop significant technology.

YD: Transition to 450mm has slowed down in the past year, however, activities are still undergoing especially at the major players. Is Orbotech also preparing for supporting 450mm and if yes, can you comment on your level of readiness and for which of your products? Have you already shipped any 450mm tools?

Sometimes I think I will be retired before 450mm systems see any HVM! We are watching the market, but see no need to accelerate from where we are. That is not to say we are ignoring it. The wafer handling aspect has already been dealt with by our automation partners. And our plasma dicing activities on framed wafers is taking our plasma source knowledge into the 450mm formats.
I don’t worry about 450mm. There is plenty happening on smaller wafers. For instance, we have seen a recent increase in 200mm demand; MEMS and power for instance is still a 200mm activity. The market at 300 and 200mm remains healthy, and we have plenty of customers and new opportunities.

Yole Développement thanks David Butler, and SPTS, for participating in this interview and will continue to watch this platform.
Stay tuned for more updates and find more information on Fan-Out and Embedded Die: Technologies & Market Trends report!


David Butler - VP Product Management and Marketing, SPTS Technologies
David Butler crop
David Butler currently serves as the Vice President of Product Marketing and Marketing at SPTS Technologies, and has more than two decades of experience in the semiconductor capital equipment and related industries. He first joined Electrotech in 1988 as a Senior Process Engineer and moved to Product Marketing for Electrotech’s PVD products. In 2004, he assumed the role of Director of Marketing for the PVD/Etch/CVD products at Trikon, becoming Vice President of Marketing for the three product lines at Aviza Technology following the merger of Aviza and Trikon.

In 2009, following the formation of SPTS Technologies, Mr. Butler was appointed VP of product and corporate marketing, overseeing all marketing efforts for SPTS’s full range of PVD, Etch, CVD and thermal products.

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