Fan-Out packaging: the most dynamic advanced packaging platform. Will it be sustainable long-term?
TSMC investment in Fan-Out Wafer Level Packaging (FO WLP) and development of InFO changed the WLP landscape. Following high volume adoption of InFO and further development of eWLB technology, a wave of new players and FO WLP technologies may enter the market. TSMC’s FO WLP solution called InFO will be used to package the Apple A10 application processor, implemented in the new iPhone 7 series.
Production starts in 2016 and represents a big change in the Fan-Out industry for several reasons:
- First of all, in terms of volume, capturing the Apple processor market is a big asset for Fan-Out technology. iPhone 7 phones are expected to be sold in more than 200 million units.
- In terms of technology capability it is also a major turn: processors require thousands of connections while the Fan-Out market was essentially focused on limited IO count applications so far.
- Eventually, the potential for market spread is very high: the Apple brand brings more interest to the Fan-Out platform.
2016 is a turning point for the Fan-Out market since Apple and TSMC changed the game and may create a trend of acceptance of Fan-Out packages. The market will actually be split in two types:
- The “core” market of Fan-Out, including single die applications such as Baseband, Power management, RF transceivers, etc. This is the main pool for FO WLP solutions and will keep growing
- The “high-density” market of Fan-Out, started by Apple APE, that will include larger IO count applications such as processors, memories, etc. This market is more uncertain and will require new integration solutions and high performing Fan-Out packages but has a very high potential.
The report contains detailed analysis of the market development including several scenarios linked to respective applications and players.
With such a high potential for the high-density Fan-Out and solid growth of the core Fan-Out, the supply chain is also expected to evolve with a considerable amount of investment in Fan-Out packaging capabilities. Several players are already offering FO WLP while many others are developing their competitive Fan-Out platforms to enter the Fan-Out landscape and enlarge their portfolio.
Apart from TSMC, STATS ChipPAC is willing to make further investments powered by JCET, ASE extends its partnership with Deca Technologies while Amkor, SPIL and Powertech are in development phase eyeing future production. Samsung is seemingly lagging behind and is considering its options to raise competitiveness.
What are the next steps of the leading Fan-Out players? This report analyzes in detail the strategies and offers of main players involved and describes potential success scenarios for all of them. It also helps to define what is Fan-Out Packaging and what are the different products and platforms, player per player, avoiding confusion already visible in the industry where many players call their solution a “Fan-Out” despite having significant differences from one to another (chip-first, chip-last, face-up, face-down, etc…).
Great potential brings a large variety of technologies. Which one will be the winning solution?
This question is investigated deeply in this report. Primarily, mobile customers have high expectations of miniaturization and higher integration while keeping costs low. This leads naturally to WLP for cost and performance and System-in-Package (SiP) solutions for integration and functionality. FO WLP has proven its ability to reach these targets. Its small form-factor and low cost capabilities shown in the first wave of acceptance, referred to as the “core” market, are now enhanced with high-integration ability of the new Fan-Out architectures shown in Figure 3. These architectures are expected to spread driven by the “High-Density” Fan-Out market. The main example available of wider integration being TSMC Fan-Out package-on-package (PoP) for Apple.
Great opportunities induce technical challenges
Along with detailed roadmaps and supply chain analysis, this report explains the technical complexity, discusses the related technical trends already showing more potential and provides a manufacturing challenge analysis. Moreover, this report also includes information on how equipment and material providers address key technical challenges of Fan-Out packaging.
Today there is a sense of urgency in developing line widths/spaces down to 2/2 um and below, developing multiple RDL layers, integrating multiple dies and dealing with subsequent warpage and yield concerns. Different processing approaches attempt to implement best practices for known good die and known good RDL to increase overall yield. Other known challenges such as die shift have also not been fully resolved yet.
As package price represents the final verdict, carrier size evolution is an important topic, both for wafers and panels, since it can help to drastically reduce the cost. Figure 4 shows that the main trend is still to keep wafer carriers but some players are already investing and developing panel-based solution. This report also focuses on the trends and challenges associated to carrier evolution.
WHAT'S NEW COMPARED TO LAST EDITION
- Overview of Fan-Out technologies available and in development
- Comparison of different Fan-Out platforms and associated markets
- Commercialization status, market adoption, forecasts and analysis update per technology
- Strategy analysis of main players and newcomers (JCET STATS ChipPAC, TSMC, ASE, etc…)
- Updated market sizes and split per application in units and revenue
- Market adoption and technology roadmaps
- Panel and wafer volume forecasts
- Roadmap of panel adoption
Objectives of the Report
This report’s objectives are to:
- Provide an overview of existing packages processed on panel
- Deliver a high-level market overview of panel packaging
- Identify panel packaging’s drivers and trends
- Offer a current status and forecast for panel packaging platforms
- Highlight key players and provide supply chain analysis