Panel level packaging players are ready for high volume production.
WHY IS THE INDUSTRY INTERESTED IN PANEL LEVEL PACKAGING?
The demand for lower cost plus higher performance, coupled with OSAT/assembly house end-customers’ desire for increasingly lower prices, has driven the semiconductor industry to develop innovative solutions. One approach to reducing overall cost is to switch from wafer and strip-level to a larger-size panel format that takes advantage of efficiency and economies of scale. Going from wafer to panel (for example 12” wafer to 18” x 24” panel) could enable cost reductions of up to 50% (if technologies are ready) and yields exceeding 90%. Panel-level manufacturing has the potential to leverage the knowledge and infrastructure of wafer-level packaging (WLP) and the PCB/flat-panel display/photovoltaic industries.
Various factors are driving Panel Level Packaging (PLP) development and encouraging diverse players from across the supply chain (including equipment and materials) to invest in panel infrastructure. On one side, the leading fabless players want OSATs to reduce the cost of highdensity FOWLP and going to large size panel is seen as the key step to significantly reducing the package price. In fact, FOPLP is on every big OSAT’s roadmap. On the other side are players whose strategy is to invest and develop PLP capability and push hard for its adoption. These players, mainly driven by the success and publicity surrounding FOWLP, are also those that:
- Missed the early FOWLP (eWLB) wave (i.e. PTI, ASE)
- Were affected by losses in the substrate business and want a new business model that utilizes their experience in substrate manufacturing (i.e. SEMeCO, Unimicron)
- Already have experience in panel processes (i.e. LCD packaging) and believe they can leverage this experience for PLP (i.e. NEPES)
- Want to develop high-density, low-cost packaging to support their front-end chip business (Samsung Electronics, Intel)
SUPPLY CHAIN: STATUS AND READINESS
Many packaging platforms can be considered panel-based, but for this report we consider only two packaging technologies to be PLP, where both RDL interconnect fabrication and further assembly are done at panel level (with panel size >300 mm x 300 mm): FOPLP and embedded die. Between the two, FOPLP is the most-discussed and the one which attracts the greatest interest of many players (including equipment and suppliers), and thus is the main focus of this report.
Lots of players have been developing FOPLP technology, but after years of development/ qualification/sampling, three players will finally enter in production in 2018: Powertech Technologies (PTI), NEPES, and SEMCO. NEPES has been in low-volume production since 2017. ASE, in partnership with Deca Technologies, is in the advanced development stage and will commence volume production in 2019/2020. Each player has its own business strategy and is working on its own FOPLP technology (panel size, leveraging different infrastructure, etc.). For example, NEPES is focused on the coarse design (>10/10 L/S), targeting automotive, sensors, and IoT applications, and will likely not explore high-density design. On the other hand, PTI and SEMCO’s long-term aim is to target mid and high-end applications that require 8/8 or less L/S. Meanwhile, Unimicron is working on a business model whereby it will manufacture the high-density RDL, with further assembly done by an OSAT partner or customer. Also, prominent OSATs like Amkor and JCET/STATS ChipPAC are currently in a “wait and see” stage, evaluating various options. They will not enter volume production before 2022.
Equipment availability for PLP is not a bottleneck today. Tools are available in the market to support various process steps in panel processing. However, certain tools that support high-density panel packaging are special and expensive. So, tool cost, not availability, is the bottleneck. For some panel-producing process steps (plating, physical vapor deposition [PVD], molding, die attach, and dicing), tools are readily available and can be adapted from the PCB, flat-panel display, or LCD industries. However, for other key process steps inherent to advanced packaging (i.e. lithography), the development of new, upgraded tool capabilities is necessary to support such steps as fine L/S patterning on panel, thick-resist lithography, panelhandling capabilities, exposure field size, and depth of focus. Over the last few years, these tools have been in development at equipment suppliers.
Equipment suppliers are adopting different strategies for entering the PLP business: acquisition (for example, Rudolph Technologies has developed PLP-focused tools based on knowledge received through its acquisition of AZORES Flat Panel Display Panel Printer); by leveraging tool experience from other businesses and upgrading it (i.e. Evatec, Atotech, SCREEN); and by organically developing PLP tools from scratch (ASM). Also, some tool suppliers have a strong position in the FOWLP market but are skeptical of the PLP business and thus are taking a wait-and-see approach (Ultratech, Applied Materials, Lam Research).
TECHNICAL CHALLENGES AND HIGH VOLUME MANUFACTURING ROADMAP FOR PANEL LEVEL PACKAGING
Certain criteria must be fulfilled and certain challenges overcome for FOPLP’s broad adoption. These criteria/ challenges are linked to large capex investment, standardization, multisource availability, and most importantly, market availability to keep the panel line running. There are technical challenges too, such as warpage control, die placement accuracy, and the fabrication of sub 10/10um line, etc. on large panels.
Standardization of the panel size and assembly process is the biggest hurdle for FOPLP adoption. Each player is developing its own process using different panel sizes and infrastructure (PCB/LCD/WLP/PV/Mix) catering to specific applications and customers. In this scenario it’s very difficult for end-customers to multisource. Also, it’s not profitable for equipment suppliers to design and manufacture equipment according to different customers’ requirements.
Given the technical challenges that will adversely affect the yield, the FOPLP that go into HVM production will support a relatively simple design: >10/10 umL/S, 15 x 15mm2 package size, and multi-die SiP integration.
- Updated 2017 - 2023 Panel Level Packaging (PLP) forecast, by packaging platform
- Updated, in-depth analysis of potential applications that could drive the PLP business
- Update on the activities of the various players involved in PLP
- Updated “Equipment and Materials” section: in-depth coverage of the processes, tools, and materials for PLP, as well as technical challenges, key suppliers, and competitive benchmarking
- Equipment suppliers’ PLP-specific strategies
- Different players’ PLP technology development, readiness, and adoption time
- Comprehensive analysis of the various manufacturing challenges for PLP adoption
- Revised technology roadmap (based on the 2017 - 2023 high volume manufacturing technology roadmap)
OBJECTIVES OF THE REPORT
- Provide an overview of panel package technologies
- Describe the key applications that could use the panel infrastructure
- Highlight panel package solutions and the players supporting these packages
- Identify the current and future industrial players for each packaging technology, based on panel level
- Provide market data and forecasts for panel products
- Explore each segment’s competitive landscape