Advanced packaging: the rising wave of the semiconductor industry

This article has been written by Yole Développement’s Business Unit Manager, Thibault Buisson for Evatec magazine, LAYERS, 2016 edition. The “More than Moore” market research and strategy consulting company invites you to discover the advanced packaging ecosystem and its evolution…

The introduction of new functionality, miniaturization and cost down- Advanced Packaging has the potential to offer it all. Thibault Buisson from Yole Développement reviews the prospects for the technologies within the Advanced Packaging market over the next 5 years.


For more than five decades the semiconductor industry has followed Moore’s law, driving miniaturization of transistors and scaling of the CMOS technology to smaller and more advanced technology nodes while at the same time reducing the cost significantly. This miniaturization process has resulted in higher performance devices, increased I/O density and a more efficient utilization of the silicon space.

The semiconductor industry is expected to start another cycle that will be driven largely by consumer products and the Internet of Things (IoT). Although performance and cost were the 2 main drivers historically, todays’s growing portfolio of applications and a higher diversity of products means that the ability to incorporate various new functions within a system and product, while continuing the miniaturization,and cost down trends, is becoming even more challenging. Building various functionalities within the chip was traditionally done using a system-on-chip (SoC) type architecture, but its becoming more and more difficult and costly to use the same structure for more complex systems where integration of various disparate technologies is required. While the scaling process continues and more advanced technology nodes are being developed, the investment and developmental time required are increasing significantly.


To overcome these limitations, the industry has turned its attention to the alternative approach of Advanced Packaging that can address both current and future market demands with more flexible manufacturing and integration approaches, bringing new technologies faster to market at a lower cost, and still addressing further performance increases and miniaturization.

Its no surprise that a significant level of activities are currently taking place in this segment. Advanced Packaging brings a broad range of platform and interconnect technologies that can address requirements across various markets, from low to mid and high end applications for consumer, computing, industrial, automotive, renewable energy, military and aerospace, etc.

Packaging of devices was done traditionally with lead-frames and wirebonding, but newer advanced packaging technologies have been developed and commercialized addressing both single and multiple die integration. There are several platforms available today in the market: platforms using encapsulation based technologies (especially applied for MEMS and sensors, wafer level optics), packages with electrical redistribution layers (either within the die, as would be the case of fan-in, or extending outside the die in case of fan-out), embedding dies within organic substrates, flip chip bumped packages using intermediary substrates and stacked devices using through-silicon-via interconnect technologies. The suitability of each of these platforms and market adoption will depend on the final product and application needs.

Full article is available on evatec website – LAYER 2016 magazine, advanced packaging section.

To read the full magazine, click: LAYER 2016 magazine.

This article has been written in collaboration with Rozalia Beica, formerly CTO & Business Unit Director of Yole Développement.



Related report:

Status of the Advanced Packaging Industry 2015 (Yole Développement, Nov.2015)

IoT driven semiconductor industry consolidation is reflecting into a highly dynamic advanced packaging landscape. Demand for advanced packaging and market size is increasing.

Focus is turning to integration and wafer level packages to enable a functionality driven roadmap and revive the cost/performance curve… More








Related presentations

Login to access our presentations

Liked this post?

Share it on your social networks