Chipmakers getting serious about integrated photonics

This technology could enable the next wave of Moore’s Law. What’s needed to make that happen?

Integrating photonics into semiconductors is gaining traction, particularly in heterogeneous multi-die packages, as chipmakers search for new ways to overcome power limitations and deal with increasing volumes of data.

Power has been a growing concern since the end of Dennard scaling, which happened somewhere around the 90nm node. There are more transistors per mm², and the wires are thinner, which increases resistance and capacitance and generates heat. Alongside of that, the amount of data that needs to be processed and moved continues to grow, so various processing elements, memories and I/Os are being utilized more intensively than in the past. This makes it harder to move data, to deliver enough power where it is needed, and to dissipate the heat.

Photonics offers a potential solution. In fact, it could provide a step-function improvement, opening the door to new applications that are limited by fixed power budgets and copper interconnects.

The cost of communications using copper is starting to become prohibitive,” says James Pond, director of product management at Ansys. “The challenge with electrical interconnect is that as you go up in performance, or up in reach, your power costs go up. The industry is getting to the point where electrical interconnects will consume your power budget in its entirety, and that’s going to happen within a few years.

Until recently, this was prohibited by cost. “It gets to be really interesting when the cost of photonics crosses below the cost of copper,” says Gilles Lamant, distinguished engineer at Cadence.

Are we close to that point? To answer that question, it is necessary to look at other developments within the industry.

The reticle limit defines the maximum size that a lithography machine can etch. For 193nm immersion steppers, which are used to produce a large proportion of chips, that limit is 33 x 26 — a little over 800mm². At the same time, Moore’s Law is slowing in terms of cost effectiveness for many companies or design types. That means the number of transistors that can be economically fabricated on a single piece of silicon is reaching its limit.

The next phase of Moore’s Law requires that devices start becoming assemblies of multiple dies, and the industry has been investing in this technology. Proprietary versions of it are found in most high-end CPUs and GPUs, FPGAs, and AI processors. As the industry increases adoption, problems are being solved, costs are coming down, and that is enabling larger potential markets.

Heterogeneous integration of multiple die points to the notion of chiplets. These are pre-designed and fabricated pieces of functionality that can be assembled in a package in much the same way as chips are assembled on a PCB. There are several challenges that have to be overcome in the industry before this becomes a broadly adopted reality. Some of them are technical, others financial or legal, and some of them relate to the creation of standards that can ensure a large enough market for these standardized pieces.

Chiplet technology also will help heterogenous integration of things other than electronics (see figure 1). We have already seen video sensor devices that are a combination of an optical layer and an electronic layer being fused together using wafer bonding. The volumes are enormous, and the technology well proven since 2016.

Source: https://semiengineering.com/

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