3D Packaging is transforming the world of Semiconductor Packaging – Webcast

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3D Packaging plays a pivotal role to re-invent integration architectures

Although Moore’s Law has remained alive for over five decades, it is no longer cost-efficient. When it comes to advanced lithographic nodes, lesser manufacturers can keep up. Now there are only three leading-edge players, Intel, Samsung and TSMC. The industry is now diligently using advanced packaging technologies to put multiple advanced and/or mature chips in a single package, which is also known as heterogeneous integration. Together with 3D packaging this extends Moore’s Law at system-level.

Times have changed. The industry is seeking alternatives to design and manufacture the latest Systems on Chips (SoCs) using System in Package (SiP) and chiplet-based approaches by leveraging High-End Packaging to mix both the latest and mature nodes. 2.5D/3D packaging is accelerating into new technical breakthroughs for 3D Interconnect Density (3D ID). Such is the crucial role of 3D packaging in the semiconductor industry.

The future points towards higher interconnectivity density and increased power efficiency with each generation. Hybrid bonding is gaining momentum as it races to be the new permanent bonding method in 3D device stacking. The technology allows manufacturers to produce devices that have significantly high-density interconnects. 2.5D-3D stacking has been achieved using through silicon via (TSV) technology for its high electrical performance. TSV technology faces limitations in reaching very dense architectures along with complexity and added cost of TSV manufacturing. Microbumps used in heterogenous packaging also faces drawbacks as the new generation packages continue to scale. Overcoming these limitations drives device manufacturers to pursue alternative and competitive methods of device fabrication. Hybrid bonding is not only proposed as an advanced packaging solution, but it is equally used as a scaling method. Two wafers with different functionalities can be bonded together to form a compact 3D structure. As the technology matures, hybrid bonding could be highly adopted by many players for its advantages that go beyond cost. It is a key enabling technology that is valuable for wafer to wafer and equally attractive for die-to-wafer bonding. Evaluating the technology and cost benefits of hybrid bonding could outweigh its limitations as the technology matures.

Samsung’s abstract :

Scaling down of transistor is helping System on Chip (SoC) integrating more functions on a monolithic chip, but SoC is not meant for heterogeneous integration with other devices including DRAM memory. In this presentation, Samsung Foundry CUBE technologies will be introduced for heterogeneous integration. CUBE is a passive/active interposer device connecting heterogeneous chips and/or chiplets horizontally and vertically for HPC, 5G, Mobile, AR/VR, IoT, Networking and AI applications.

Related reports

High-End Performance Packaging: 3D/2.5D Integration 2020
Intel Foveros and TSMC 3D SoIC are competing head-to-head for high-end packaging – How will Samsung react ?


SPEAKERS

  • Favier Shoo

    Team Lead Analyst, Packaging

  • Belinda Dube

    Technology & Cost Analyst

  • Max Min

    Director from Samsung Foundry

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