Semiconductor industry is at a turning point, the slowdown in CMOS scaling and escalated costs has prompted the industry to rely on IC packaging industry to extend the benefits of more-than-More era. The packaging industry has been undergoing radical change in the past few years as many organizations are exploring various options to integrate dies. However, for the purpose of IP reuse strategy and reducing the overall costs, chiplet based heterogeneous integration has emerged as a viable solution. Depending on the circuit partitioning scheme and strategy, various heterogeneous integration strategies and technologies may be utilized to achieve lower power and costs as well as faster time to market to deliver the traditional benefits of CMOS scaling. Packaging is now becoming an integral part of the system where assembly and test at 50um bump pitch and choice of substrates with multiple RDL layers with less than 1um L/S is as important as ever. Similarly, back-end equipment makers are gearing up to align with the new specifications and requirements for heterogeneous integration. In this talk, we will explore the technologies, vision and path to move forward as the semiconductor industry tries to cope with the slowdown in CMOS scaling.

Higher performance SoC (CPU, GPU, FPGA, ASIC), chiplets and High Bandwidth Memory (HBM) have been introduced to high performance computing for the raising AI, machine learning and deep learning applications. This brings big challenges to package technology, such as higher power consumption, larger die size and lager package size, better electrical SI/PI, higher density connection, etc. This is also driving various package evolution from structure, process, materials and even design methodology. This presentation will discuss Amkor’s high-performance package solutions, including single chip FCBGA, multi-chip module FCBGA, HDFO (High Density Fan-Out) and 2.5D Heterogeneous packages for the coming era of AI.

High performance computing is the power behand recent progress in artificial intelligence, self-driving cars, 5G, medical research, robotics, smart cities, etc.  

Currently HPC structure is based on von Newman architecture where the memories are placed close to the processors for timely data communication. Silicon based interposer 2.5 D technology is widely used in the HPC packaging. High performance processor like GPU/CPUs are placed near memories such as HBM2. Companies like Nvidia, AMD, Xilinx and others are adoption this technology to their high end products. But because of the lossy nature and the cost of the silicon interposer, efforts have been made to replace silicon interposer by other types materials such as glass. The other approach is combining interposer and substrate to form an “integrated substrate”. EMIB is the packaging solution for HPC by Intel. Other emerging packaging solution such as 2.1D, 2.3D by Shinko and eHDF (embedded High Density Film) by SiPlus are working hard to provide alternative “integrated substrate” solutions to HPC packaging.

More types beside CPU will be needed in the future HPC systems. Processers structure like CPU, GPU, FPGA and accelerators are all needed in future HPC. They will be communicated to each other by protocols such as CCIX or CXL recently promoted by Intel. Hence, large area and fine line Interposer/substrates are needed for future Multi dies heterogeneous integration of HPC.

On the other hand, as semiconductor is progressing to finer nodes, the of SOC pricing is skyrocketing. One alternative is using the Chiplets solution. Substrates with submicron lines and finer bump pitches below 10µm are needed to integrate individual chiplets. There are still a lots of development work need to be done in this area. However once successful, the benefit to the current industry is enormous.

With evolution of communication technology, 5G development and implementation is driving the deep integration of AI, HPC, and IIoT. The nature of this integration is pushing for high bandwidth and low latency for faster computing / analysis and shorter communication / feedback cycle . The major package platform for HPC in cloud / datacenter and edge computing is fundamentally fcBGA. It is being driving towards even larger package size, finer pitch, and better thermal management in heterogeneous integration to cope with Si node progress driven by Moore’s Law and its associated higher power density. In this presentation, below aspects are discussed:

•  Flip Chip Markets & Applications
• fcBGA package structure and size
• fcBGA process flow
• fcBGA thermal management
• Advance in fcBGA and its trend

Since 5G network age is coming, 5G application totally redefine router / switch technology development, especially for the enterprise level of router / switch, which requires the wider bandwidth to proceed the larger transmission signal. It is forecasting that the bandwidth requirement would enhance to 25.6T,and even over 50T. The homo / hetero integration package technology would support the advanced router / switch development. Despite of 2.5D and 3D package to apply in, FO-MCM technology with chip last assembly and more dies integration in one package would be the critical package type for quality and cost benefit to promote the transmission devices and earn the more advantages.

While Moore’s Law is hitting its limitation both physically and from an economics standpoint, the semiconductor industry turns to advanced packaging technologies to increase performance and integration while lowering costs. Brewer Science was one of the first companies to consider temporary wafer bonding as an enabling technology for ultrathin wafer handling. Nowadays, temporary bonding is not only used for wafer thinning and backside wafer processing at high temperatures and high vacuum levels, but also for handling of new types of packaging substrates such as reconstituted wafers and panels that easily deform under thermal stress. We understand that it is impractical, if not impossible, to cover the entire range of market needs with one material set or type. Therefore, we have adopted a portfolio approach to material development and utilize many different platforms to address the needs of this fast-paced market. This presentation will illustrate a novel dual-layer approach. Our dual-layer materials combine a thin thermoplastic bonding material and a thick thermoset bonding layer, which prevent material flow at high temperatures after curing. When designing the dual-layer bonding system, careful attention was placed on material performance for very high-temperature, high-stress applications, while also considering very thin wafer (20 µm and below) handling. There are 2 layers in the system to allow more room to tailor the material properties to target enhanced performance. For example, the thermoplastic layer was designed to obtain a conformal coating with good adhesion to the device as well as the curable layer. The thermoset material was carefully designed to obtain target thickness, bonding, and curing conditions. Combining these two layers, the dual-layer bonding system provides enhanced mechanical and thermal properties. The dual-layer bonding system was developed to aid thin wafer handling (TWH) processes within multiple market segments including: III-V compound semi, power, 3DIC, memory, eWLB, MEMS, and other FOWLP segments – all of which have stringent requirements with respect to adhesion, low total thickness variation (TTV), temperature stability, performance, and form factor. The advantages of the dual-layer bonding system include increased throughput, ease of cleaning after processing and the thinning to sub-20 µm with good uniformity.

Transistor scaling has historically been the primary driver of Moore’s Law. However, as the cadence of traditional front end scaling has slowed and the returns have diminished, the semiconductor industry has increased focus on the deployment of innovative packaging solutions. 3DIC integration by stacking die using TSVs (Through Silicon Vias) is one of the major technology platforms being adopted to achieve system-level PPAC (Power, Performance, Area, Cost) objectives. 3DIC has already been utilized for stacked DRAM in HMC and HBM applications. Now, the semiconductor industry is turning to 3DIC with increased interconnect density for memory-on-memory, memory-on-logic, and logic-on-logic. Hybrid bonding is being developed as an alternative to thermo-compression bonding with microbumps. As 3DIC processes move into these applications with higher-density interconnects and with hybrid bonding, inspection and metrology solutions must address TSV scaling and quality control requirements to enable manufacturers to achieve yield ramp objectives. KLA has developed new inspection and metrology technologies to provide the industry with high sensitivity, high resolution, high accuracy solutions for process control in increasingly advanced 3DIC applications.

As a leading provider of semiconductor packaging and electronic assembly solutions, Kulicke and Soffa (NASDAQ: KLIC) offers full range of solutions to memory products, which includes traditional packaging (die stacking and wire bonding), advanced packaging (HBM,HMC), SIP, module assembly and POP. Memory products have tremendously grown since 2016. The new technology derives from big data/cloud computing, to IoT,  to AI, 5G, and smart cities; all of them require the support of more advanced memory products. With this emerging trend, K&S continues to put tremendous efforts and resource to develop our key competence in advanced manufacturing technologies related to memories packaging solutions. Another trend is also die handling in advance thin packages used in mobile devices. Thermal compression bonding has also been developed to address memory applications specifically for HBM and HMC.  

In today’s world, as rapid expansions in AI and IoT applications, typically represented by High Performance Computing and Edge Computing technologies, consumer products are smaller, more powerful and complex, and requiring system solutions. The new focus on the semiconductor design and therefore the packaging technologies are encountering many new challenges by those requirements. One of the key solutions in Packaging is the SiP technology. In this presentation, the trend of SiP technology developments is introduced. The current and future SiP technologies in varies of applications, such as the HPC and autonomous automotives are discussed

Within the whole industry, all electric devices also functional modules require smaller size and higher integration,  AT&S as world’s high end HDI and substrate manufacture company would like to promote the All in one package solution which utilize current advanced mSAP/substrate/ECP technology and target for future full turn key solution.

In the last few years, radio frequency (RF) applications have driven the advanced electronics packaging market to encompass different sectors. With products such as Automotive Radar, High-End Smartphones or WiGig devices, the RF packaging market is expected to grow in every sector. Wafer-level packaging (WLP), 3D through-silicon vias (TSVs), SiPs (Systems-in-Packages), and electromagnetic interference (EMI) shielding are key enablers for heterogeneous integration in segments where RF devices require small form factors, high speed operation and a high degree of isolation. Also, cost efficiency is critical.

Based on images extracted from teardowns and physical analyses of several consumer RF devices, we will demonstrate the present power of RF packaging solutions for manufacturers such as Qualcomm, Broadcom, and Skyworks, from the manufacturing cost to the functional integration. We will extract some clues for future fifth generation (5G) and millimeter wave (mmWave) applications. We will also present how these companies manage to provide highly integrated SiPs featuring several advanced packaging technologies cost-effectively.

The first release of 5G standard, 3GPP R15, is finalized in time in June 2018. Since then, the whole wireless communication industry started counting down to the commercialization of the 5G. The achievements from different segments of the industry chain, chips, terminals, demos of equipment vendors, field trial of the operators, etc., hit the media timely and more and more frequently. In the other hand, there does exist “anti” voices that doubted the benefits, ambitious aims, aggressive commercialization plan, etc. of 5G. This talk will share with the audience a latest collection of 5G progress from various aspects, as well as the observed challenges on the way ahead.

While IoT solutions deployment surge continuously across diverse business sectors with a wide range of services, new emerging technologies are paving innovative approaches to make IoT implementation more efficient and effective. The huge amount of complex raw data produced by IoT devices is driving the trend towards decentralization of data. Advanced approaches are shifting data processing and analytics, and even some level of decision making to the point of origin - the so called IoT edge. Bin Fu takes a closer look at how smarter sensors can contribute to that trend, from the perspective of a sensor solution innovator.

Both the software/hardware for AI/IoT applications are contributing to our ever increasing demand of performance and capability for future life in smart home, city, factory, … etc. Interestingly, by utilizing the AI/IoT capability, development of ICs for AI/IoT applications are also being accelerated and revolutionized toward concurrent design, co-optimization in technology, manufacturing with full automation and big-data analysis, and advanced packaging for 3D heterogeneous integration.

As the demand for smaller and thinner form factor wafer for low- and high-end applications as well as the need for lower production costs increases. Fan-out wafer level packaging technology comes into the surface as one of the solutions. FOWLP has caught the attention of the big players in IC packaging and has developed several different structures such as eWLB from Infineon, SLIM and SWIFT from Amkor, M-Series from Deca and InFo from TSMC. This type of packaging has been used for a wide range of applications such as Baseband Processors, PMICs, Connectivity Modules for IoT, CODECs and many more. With its versatility, it opened the potential utilization for multi-die configuration or heterogenous integration like System in Package (SiP). With all the advancement and varying structure, the semiconductor packaging industry continues to face top yield issue typical for FO packages; warpage and die placement accuracy. Warpage remains a bottleneck issue requiring a robust solution to enable high volume with high yield manufacturing. This issue occurs due to the CTE mismatch of the silicon and molding compound encapsulant when the wafer is subjected to thermal treatment. However, applying the correct thermal treatment process will also result to warpage profile of <1mm which will allow succeeding processes to run smoothly. The idea is to treat the wafer with the temperature above its Tg until the mold compound softens and transporting it into a chuck of lower temperature while retaining its flatness, flexibility and high temperature prior reaching the lower temperature state. As the wafer sits on the cooler stage and the vacuum is pulled, it conforms to the flatness of the stage. The transport from the debond stage and the cool stage plays a significant role requiring several critical items; the temperature must be uniform to ensure all areas achieve thermal equilibrium at one time to reduce complex warpage profile, the transport from the high temperature chuck to low temp chuck needs to be fast to retain the temperature of the wafer and the handling needs to not induce contour to the wafer as it will easily conform to the shape where the temperature is low. This paper targets to address all critical items to produce low warpage wafers post debonding process as well as independently doing warpage adjust on wafers causing yield and manufacturing hiccups.

It is well known that 2.5D and 3D stacking technologies are currently the main solutions that can meet the required performance of applications like artificial intelligence (AI) and data center. For today’s high-end market segment, the most popular 2.5D and 3D integration technologies on the market are based on TSV for 3D stacked memory, and TSV interposer for heterogeneous stacking. Currently on the market, high bandwidth memory (HBM) and CIS are fabricating with through silicon via (TSV) technology. The recently emerged TSV-less technology consists of two groups: “with substrate” and “embedded in substrate”. Hybrid bonding can bridge the two main categories of “with TSV” and “without TSV”. This popular technique can be a complimentary or competition to TSV technology.

As a national center for advanced packaging, testing and system integration, NCAP aggressively pursues research and development through close collaboration with industry, colleges and research institutions. NCAP’s roadmaps comprise of 2.5D & 3D TSV and integration technologies, including TSV, bumping, via-reveal and chip-stacking, high density wafer level packaging, and SiP product application and development, and verification and development of related advanced materials and equipment for microelectronics packaging.

Wafer level fanout technology has drawn much industry’s attention since it was first adopted into the high-end AP application a few years ago. This technology can enable wafer level system-in-package (SiP), during which multiple heterogynous chips are integrated together in a re-constructed wafer to form a dedicated packaging module. The fanout technology balanced well the cost and performance, and enabled integrating to be the smallest packages. NCAP has started multiple R&D projects to study the packaging design, reliability, materials verification, and various process flows. We present our recent work on various fanout cases, such as single chip packaging, and the development of multiple chips integration.

This presentation will provide a broad overview of the Smart MEMS Sensors for Internet of Things (IOT) within the TDK-InvenSense portfolio along with the discussion of emerging applications. We will discuss how these sensors are driving new use cases & trends for developing new package architectures for MEMS applications. The implications of these trends like sensor fusion & integration approach to combine multiple sensors in single package; the trend towards further miniaturization as well new use cases like water proof package technologies etc. will be reviewed in the context of developing new materials & processes as well as managing trade-offs to meet package performance, quality & cost goals.

Ubiquitous display means display will be everywhere in the future life. During this golden age of display technology, the flexible AMOLED technology will face plenty of opportunities and difficult challenges at the same time. Microled may be another potential candidate for the future display technology.

Moore's law has been pushing the industry on the road of scaling to a new height where alternative solutions were needed. In order to achieve both the form-factor and manufacturing cost, IC design companies are looking beyond SOC's for various reasons. In the case of sensors, it might be more cost effective to use different technology nodes for analog and signal processing for example. These different chips could be integrated using today's packaging scaling approaches to realize better performance, design flexibility and lower cost structure. We will probably seeing more designs to integrate processors, signal processors, cache, sensors, photonics, RF, and MEMS for the new generation of IOT  devices in the future.