Advanced packaging: at the heart of innovation
Advanced packaging is driven by the wind of changes…
Be part of our Advanced Packaging & System Integration Technology Symposium!
Please notice that the registration platform will close on Friday April 19
(6:00 PM – Shanghai Time | 12:00 PM – Paris Time | 6:00 AM – New York Time)
You will be able to register on site at the registration desk from Monday April 22!
For the 5th edition, NCAP and Yole Développement combine their expertise to build an innovative program dedicated to the advanced packaging industry – during one day and a half, meet the leading executives and gain an in-depth understanding of the market evolution!
It is a fact, Advanced packaging is at the heart of innovation. Mega-trend applications are bringing new challenges, and leading advanced packaging companies from all over the world will come to exchange ideas on their vision and future perspectives at the Advanced Packaging & System Integration Technology Symposium.
Yole Développement and NCAP have created an unprecedented program to understand the status of the advanced packaging industry and help the companies to be part of the ‘tomorrow’ industry. The Advanced Packaging & System Integration Technology Symposium is unique. Don’t miss it!
This year, the location will change, it will thus take place in Shanghai, China, from April 22PM to 23, 2019, prior to NEPCON China 2019.
During one day and a half, all packaging aspects, including Panel Level, Fan Out, System in Package, Advanced Substrates and 3D Technology, will be discussed. A focus on key applications such as AI, HPC, memory & computing, transportation (48V, EV/HEV, embedded die packaging platform, PCB, advanced substrates…), 5G and consumer (WLP and Fan-Out platforms)… will be at the heart of the conference:
AI – HPC
2.5D and 3D stacking: are these the only technologies that meet AI and data center requirements?
MEMORY & COMPUTING
Memory back-end manufacturing: who will benefit the most, and how, from the technology & business changes?
TRANSPORTATION
Infotainment, ADAS and electrification: will they reshape the automotive packaging industry as expected?
5G
How will advanced packaging solution suppliers fulfill performance requirements and complex heterogeneous integration needs?
CONSUMER
Will Fan-Out packaging continue to cannibalize and put flip-chip and advanced substrate manufacturers out of business?
New this year
During this Shanghai edition, Yole Développement’s packaging and substrate analysts invite you to get a deep understanding of the industry evolution and technology issues in semiconductor integration. With two dedicated market briefings focused on AI & HPC, memory and computing, transportation, consumer and 5G, they will describe the new ecosystem currently emerging and pushed by the needs of innovative and disruptive technologies. Yole Développement’s experts will point out the industry evolution and its consequence at each step of the supply chain.
The advanced packaging is also driven by the wind of changes, due to the impressive impact of the megatrends. Yole and NCAP China have decided to combine their expertise this year again to propose the Advanced Packaging & System Integration Technology Symposium in Shanghai, prior NEPCON China. This Shanghai edition will be the place to be to understand the industry evolution and measure the impact of the megatrends.
Agenda now unveiled !
The program is now avalaible (see below in the agenda section). For more information, please contact Fanny Vitrey (vitrey@yole.fr)
The structure of the symposium will allow attendees to get valuable insights into the advanced packaging industry as well as provide unprecedented opportunities for meeting with industry leaders…
Networking sessions during the all event. Get the opportunity to exchange with all the leading players in the advanced packaging industry.
Sponsorship opportunities available
Sponsoring the Advanced Packaging & System Integration Technology Symposium is a prime opportunity to put your company in front of more than 180 of the key industry players and decision makers of the industry. Different levels of opportunities to suit your needs – Discover our offers now
For more information, please contact Camille Veyrier (veyrier@yole.fr)
Travel and venue
The symposium will be held at the Grand Mercure Shanghai Century Park, Shanghai – Website
For any discount rates, please contact Sean Ye, Catering & MICE Sales Manager : 86 136 51 88 8934 / eventexec1@grandmercure-shanghai-centurypark.com.
Kind reminder to the overseas visitors: China visa are required to all the overseas passport holders for entry into Chinese territories. Visa Application may take a long period, and we kindly remind you to apply for the China visa as early as possible. If you need invitation letter, please contact xuyansun@ncap-cn.com or xiaoyunzhang@ncap-cn.com or download it here.
For more information, please contact Fanny (vitrey@yole.fr)
Agenda
April 22, 2019
Registration
Welcome and Introduction
Market Briefing by Yole Développement
Market & Trends in High Ends Packaging
Emilie Jolivet & Thibault Buisson
Yole Développement
Session 1: AI - HPC
Keynote: Path to Move Forward
Farhang Yazdani
President & CEO - BroadPak
Semiconductor industry is at a turning point, the slowdown in CMOS scaling and escalated costs has prompted the industry to rely on IC packaging industry to extend the benefits of more-than-More era. The packaging industry has been undergoing radical change in the past few years as many organizations are exploring various options to integrate dies. However, for the purpose of IP reuse strategy and reducing the overall costs, chiplet based heterogeneous integration has emerged as a viable solution. Depending on the circuit partitioning scheme and strategy, various heterogeneous integration strategies and technologies may be utilized to achieve lower power and costs as well as faster time to market to deliver the traditional benefits of CMOS scaling. Packaging is now becoming an integral part of the system where assembly and test at 50um bump pitch and choice of substrates with multiple RDL layers with less than 1um L/S is as important as ever. Similarly, back-end equipment makers are gearing up to align with the new specifications and requirements for heterogeneous integration. In this talk, we will explore the technologies, vision and path to move forward as the semiconductor industry tries to cope with the slowdown in CMOS scaling.
High Performance Packaging for AI
John Lee
Sr. Director, Strategic Marketing, Greater China Sales & Marketing - Amkor Technology
Higher performance SoC (CPU, GPU, FPGA, ASIC), chiplets and High Bandwidth Memory (HBM) have been introduced to high performance computing for the raising AI, machine learning and deep learning applications. This brings big challenges to package technology, such as higher power consumption, larger die size and lager package size, better electrical SI/PI, higher density connection, etc. This is also driving various package evolution from structure, process, materials and even design methodology. This presentation will discuss Amkor’s high-performance package solutions, including single chip FCBGA, multi-chip module FCBGA, HDFO (High Density Fan-Out) and 2.5D Heterogeneous packages for the coming era of AI.
Substrate Solutions for AI and HPC
Dr. Dyi-Chung Hu
CEO - SiPlus
High performance computing is the power behand recent progress in artificial intelligence, self-driving cars, 5G, medical research, robotics, smart cities, etc.
Currently HPC structure is based on von Newman architecture where the memories are placed close to the processors for timely data communication. Silicon based interposer 2.5 D technology is widely used in the HPC packaging. High performance processor like GPU/CPUs are placed near memories such as HBM2. Companies like Nvidia, AMD, Xilinx and others are adoption this technology to their high end products. But because of the lossy nature and the cost of the silicon interposer, efforts have been made to replace silicon interposer by other types materials such as glass. The other approach is combining interposer and substrate to form an “integrated substrate”. EMIB is the packaging solution for HPC by Intel. Other emerging packaging solution such as 2.1D, 2.3D by Shinko and eHDF (embedded High Density Film) by SiPlus are working hard to provide alternative “integrated substrate” solutions to HPC packaging.
More types beside CPU will be needed in the future HPC systems. Processers structure like CPU, GPU, FPGA and accelerators are all needed in future HPC. They will be communicated to each other by protocols such as CCIX or CXL recently promoted by Intel. Hence, large area and fine line Interposer/substrates are needed for future Multi dies heterogeneous integration of HPC.
On the other hand, as semiconductor is progressing to finer nodes, the of SOC pricing is skyrocketing. One alternative is using the Chiplets solution. Substrates with submicron lines and finer bump pitches below 10µm are needed to integrate individual chiplets. There are still a lots of development work need to be done in this area. However once successful, the benefit to the current industry is enormous.
Title: Coming Soon
Wang Hougong
Vice President, General Manager of PVD Divison - NAURA
Coffee break - Networking time
Session 2: MEMORY & COMPUTING
Advance in High Performance Flip Chip Packaging
Yaojian Lin
Vice President - JCET
With evolution of communication technology, 5G development and implementation is driving the deep integration of AI, HPC, and IIoT. The nature of this integration is pushing for high bandwidth and low latency for faster computing / analysis and shorter communication / feedback cycle . The major package platform for HPC in cloud / datacenter and edge computing is fundamentally fcBGA. It is being driving towards even larger package size, finer pitch, and better thermal management in heterogeneous integration to cope with Si node progress driven by Moore’s Law and its associated higher power density. In this presentation, below aspects are discussed:
- Flip Chip Markets & Applications
- fcBGA package structure and size
- fcBGA process flow
- fcBGA thermal management
- Advance in fcBGA and its trend
Heterogeneous Integration Package of IoT Applications
David Wang
Manager Product Application Engineering and Corporate R&D - SPIL
Since 5G network age is coming, 5G application totally redefine router / switch technology development, especially for the enterprise level of router / switch, which requires the wider bandwidth to proceed the larger transmission signal. It is forecasting that the bandwidth requirement would enhance to 25.6T,and even over 50T. The homo / hetero integration package technology would support the advanced router / switch development. Despite of 2.5D and 3D package to apply in, FO-MCM technology with chip last assembly and more dies integration in one package would be the critical package type for quality and cost benefit to promote the transmission devices and earn the more advantages.
Dual-Layer Temporary Bonding System for Advanced Packaging
Dongshun Bai, Ph.D.
Deputy Business Development Director of the Wafer-Level Packaging Materials Business Unit - Brewer Science
While Moore’s Law is hitting its limitation both physically and from an economics standpoint, the semiconductor industry turns to advanced packaging technologies to increase performance and integration while lowering costs. Brewer Science was one of the first companies to consider temporary wafer bonding as an enabling technology for ultrathin wafer handling. Nowadays, temporary bonding is not only used for wafer thinning and backside wafer processing at high temperatures and high vacuum levels, but also for handling of new types of packaging substrates such as reconstituted wafers and panels that easily deform under thermal stress. We understand that it is impractical, if not impossible, to cover the entire range of market needs with one material set or type. Therefore, we have adopted a portfolio approach to material development and utilize many different platforms to address the needs of this fast-paced market. This presentation will illustrate a novel dual-layer approach. Our dual-layer materials combine a thin thermoplastic bonding material and a thick thermoset bonding layer, which prevent material flow at high temperatures after curing. When designing the dual-layer bonding system, careful attention was placed on material performance for very high-temperature, high-stress applications, while also considering very thin wafer (20 µm and below) handling. There are 2 layers in the system to allow more room to tailor the material properties to target enhanced performance. For example, the thermoplastic layer was designed to obtain a conformal coating with good adhesion to the device as well as the curable layer. The thermoset material was carefully designed to obtain target thickness, bonding, and curing conditions. Combining these two layers, the dual-layer bonding system provides enhanced mechanical and thermal properties. The dual-layer bonding system was developed to aid thin wafer handling (TWH) processes within multiple market segments including: III-V compound semi, power, 3DIC, memory, eWLB, MEMS, and other FOWLP segments – all of which have stringent requirements with respect to adhesion, low total thickness variation (TTV), temperature stability, performance, and form factor. The advantages of the dual-layer bonding system include increased throughput, ease of cleaning after processing and the thinning to sub-20 µm with good uniformity.
Inspection and Metrology Challenges for 3DIC Interconnect Scaling
Kevin Khoo
Marketing Director, Advanced Packaging, LS-SWIFT Division, Global Products Group – KLA Corporation
Transistor scaling has historically been the primary driver of Moore’s Law. However, as the cadence of traditional front end scaling has slowed and the returns have diminished, the semiconductor industry has increased focus on the deployment of innovative packaging solutions. 3DIC integration by stacking die using TSVs (Through Silicon Vias) is one of the major technology platforms being adopted to achieve system-level PPAC (Power, Performance, Area, Cost) objectives. 3DIC has already been utilized for stacked DRAM in HMC and HBM applications. Now, the semiconductor industry is turning to 3DIC with increased interconnect density for memory-on-memory, memory-on-logic, and logic-on-logic. Hybrid bonding is being developed as an alternative to thermo-compression bonding with microbumps. As 3DIC processes move into these applications with higher-density interconnects and with hybrid bonding, inspection and metrology solutions must address TSV scaling and quality control requirements to enable manufacturers to achieve yield ramp objectives. KLA has developed new inspection and metrology technologies to provide the industry with high sensitivity, high resolution, high accuracy solutions for process control in increasingly advanced 3DIC applications.
Advances in Memory Packaging
Chan Pin Chong
Senior Vice President, EA/APMR & Wedge Bonders Business Units - Kulicke & Soffa
As a leading provider of semiconductor packaging and electronic assembly solutions, Kulicke and Soffa (NASDAQ: KLIC) offers full range of solutions to memory products, which includes traditional packaging (die stacking and wire bonding), advanced packaging (HBM,HMC), SIP, module assembly and POP. Memory products have tremendously grown since 2016. The new technology derives from big data/cloud computing, to IoT, to AI, 5G, and smart cities; all of them require the support of more advanced memory products. With this emerging trend, K&S continues to put tremendous efforts and resource to develop our key competence in advanced manufacturing technologies related to memories packaging solutions. Another trend is also die handling in advance thin packages used in mobile devices. Thermal compression bonding has also been developed to address memory applications specifically for HBM and HMC.
Thank You and Adjourn
Networking Cocktail and Diner
April 23, 2019
Market Briefing by Yole Développement
Advanced Packaging Trends in this Era of Digital New Age
Favier Shoo & Santosh Kumar
Yole Développement
Session 3: TRANSPORTATION
Keynote: SiP Packaging Technologies, Advantages and Applications
Yifan Guo
Vice President of Engineering - ASE Group
In today’s world, as rapid expansions in AI and IoT applications, typically represented by High Performance Computing and Edge Computing technologies, consumer products are smaller, more powerful and complex, and requiring system solutions. The new focus on the semiconductor design and therefore the packaging technologies are encountering many new challenges by those requirements. One of the key solutions in Packaging is the SiP technology. In this presentation, the trend of SiP technology developments is introduced. The current and future SiP technologies in varies of applications, such as the HPC and autonomous automotives are discussed
AT&S All in One Package Solution
Lio Li
Front-End Engineering Manager/ECP Program Manager - AT&S China
Within the whole industry, all electric devices also functional modules require smaller size and higher integration, AT&S as world’s high end HDI and substrate manufacture company would like to promote the All in one package solution which utilize current advanced mSAP/substrate/ECP technology and target for future full turn key solution.
Ag Sintering a new enabling technology to improve performance of Electrical Vehicles
Tian TianCheng
Boschman Advanced Packaging Technology
Title: Coming Soon
Yole Développement
Coffee break - Networking time
Session 4: 5G
How 5G will influence and drive Advanced Packaging Technologies
René Betschart
Senior Vice President Besi Products Asia & Besi Singapore - Besi
Advanced RF Packaging Technology Trends, on the way to 5G and mmWave Applications
Romain Fraux
CEO - System Plus Consulting
In the last few years, radio frequency (RF) applications have driven the advanced electronics packaging market to encompass different sectors. With products such as Automotive Radar, High-End Smartphones or WiGig devices, the RF packaging market is expected to grow in every sector. Wafer-level packaging (WLP), 3D through-silicon vias (TSVs), SiPs (Systems-in-Packages), and electromagnetic interference (EMI) shielding are key enablers for heterogeneous integration in segments where RF devices require small form factors, high speed operation and a high degree of isolation. Also, cost efficiency is critical.
Based on images extracted from teardowns and physical analyses of several consumer RF devices, we will demonstrate the present power of RF packaging solutions for manufacturers such as Qualcomm, Broadcom, and Skyworks, from the manufacturing cost to the functional integration. We will extract some clues for future fifth generation (5G) and millimeter wave (mmWave) applications. We will also present how these companies manage to provide highly integrated SiPs featuring several advanced packaging technologies cost-effectively.
Heterogeneous Integration SiP Technology Solution for 5G Era
Yasuhiro Morikawa
Senior Manager of Global Market & Technology Strategy Division - ULVAC
Good and Bad News on the Way to 5G Era
Zhen'gang Pan
VP of New Radio Tech. - Unisoc
The first release of 5G standard, 3GPP R15, is finalized in time in June 2018. Since then, the whole wireless communication industry started counting down to the commercialization of the 5G. The achievements from different segments of the industry chain, chips, terminals, demos of equipment vendors, field trial of the operators, etc., hit the media timely and more and more frequently. In the other hand, there does exist “anti” voices that doubted the benefits, ambitious aims, aggressive commercialization plan, etc. of 5G. This talk will share with the audience a latest collection of 5G progress from various aspects, as well as the observed challenges on the way ahead.
Lunch and Networking
Session 5: CONSUMER - Part 1
KEYNOTE: Enhanced IoT Edge by Smart Sensors
Bin Fu
Head of Business Development and Marketing China - Bosch Sensortec
While IoT solutions deployment surge continuously across diverse business sectors with a wide range of services, new emerging technologies are paving innovative approaches to make IoT implementation more efficient and effective. The huge amount of complex raw data produced by IoT devices is driving the trend towards decentralization of data. Advanced approaches are shifting data processing and analytics, and even some level of decision making to the point of origin - the so called IoT edge. Bin Fu takes a closer look at how smarter sensors can contribute to that trend, from the perspective of a sensor solution innovator.
AI/IoT Era: Revolution in IC Design, Manufacturing, and Advanced Packaging
Min-hwa Chi
Senior Vice President / TD - SiEn (Qindao) Integated Circuit
Both the software/hardware for AI/IoT applications are contributing to our ever increasing demand of performance and capability for future life in smart home, city, factory, … etc. Interestingly, by utilizing the AI/IoT capability, development of ICs for AI/IoT applications are also being accelerated and revolutionized toward concurrent design, co-optimization in technology, manufacturing with full automation and big-data analysis, and advanced packaging for 3D heterogeneous integration.
An Original Technique of Warpage Adjustment for FOWLP and FOPLP while in the Thermal Debonding Process
Debbie Claire Sanchez
FOWLP Equipment Product Manager - ERS electronic GmbH
As the demand for smaller and thinner form factor wafer for low- and high-end applications as well as the need for lower production costs increases. Fan-out wafer level packaging technology comes into the surface as one of the solutions. FOWLP has caught the attention of the big players in IC packaging and has developed several different structures such as eWLB from Infineon, SLIM and SWIFT from Amkor, M-Series from Deca and InFo from TSMC. This type of packaging has been used for a wide range of applications such as Baseband Processors, PMICs, Connectivity Modules for IoT, CODECs and many more. With its versatility, it opened the potential utilization for multi-die configuration or heterogenous integration like System in Package (SiP). With all the advancement and varying structure, the semiconductor packaging industry continues to face top yield issue typical for FO packages; warpage and die placement accuracy. Warpage remains a bottleneck issue requiring a robust solution to enable high volume with high yield manufacturing. This issue occurs due to the CTE mismatch of the silicon and molding compound encapsulant when the wafer is subjected to thermal treatment. However, applying the correct thermal treatment process will also result to warpage profile of <1mm which will allow succeeding processes to run smoothly. The idea is to treat the wafer with the temperature above its Tg until the mold compound softens and transporting it into a chuck of lower temperature while retaining its flatness, flexibility and high temperature prior reaching the lower temperature state. As the wafer sits on the cooler stage and the vacuum is pulled, it conforms to the flatness of the stage. The transport from the debond stage and the cool stage plays a significant role requiring several critical items; the temperature must be uniform to ensure all areas achieve thermal equilibrium at one time to reduce complex warpage profile, the transport from the high temperature chuck to low temp chuck needs to be fast to retain the temperature of the wafer and the handling needs to not induce contour to the wafer as it will easily conform to the shape where the temperature is low. This paper targets to address all critical items to produce low warpage wafers post debonding process as well as independently doing warpage adjust on wafers causing yield and manufacturing hiccups.
Coffee break - Networking time
Session 5: CONSUMER - Part 2
Development of 2.5D /3D Integrated System and Wafer Level Fanout Technology
Daping Yao, Ph.D.
Technical Director - NCAP China
It is well known that 2.5D and 3D stacking technologies are currently the main solutions that can meet the required performance of applications like artificial intelligence (AI) and data center. For today’s high-end market segment, the most popular 2.5D and 3D integration technologies on the market are based on TSV for 3D stacked memory, and TSV interposer for heterogeneous stacking. Currently on the market, high bandwidth memory (HBM) and CIS are fabricating with through silicon via (TSV) technology. The recently emerged TSV-less technology consists of two groups: “with substrate” and “embedded in substrate”. Hybrid bonding can bridge the two main categories of “with TSV” and “without TSV”. This popular technique can be a complimentary or competition to TSV technology.
As a national center for advanced packaging, testing and system integration, NCAP aggressively pursues research and development through close collaboration with industry, colleges and research institutions. NCAP’s roadmaps comprise of 2.5D & 3D TSV and integration technologies, including TSV, bumping, via-reveal and chip-stacking, high density wafer level packaging, and SiP product application and development, and verification and development of related advanced materials and equipment for microelectronics packaging.
Wafer level fanout technology has drawn much industry’s attention since it was first adopted into the high-end AP application a few years ago. This technology can enable wafer level system-in-package (SiP), during which multiple heterogynous chips are integrated together in a re-constructed wafer to form a dedicated packaging module. The fanout technology balanced well the cost and performance, and enabled integrating to be the smallest packages. NCAP has started multiple R&D projects to study the packaging design, reliability, materials verification, and various process flows. We present our recent work on various fanout cases, such as single chip packaging, and the development of multiple chips integration.
Advanced Packaging of Smart MEMS Sensors for Internet of Things (IOT) – Challenges & Opportunities
Vijay Wakharker
Manager of Research & Development - Advanced MEMS Packaging - TDK InvenSense
This presentation will provide a broad overview of the Smart MEMS Sensors for Internet of Things (IOT) within the TDK-InvenSense portfolio along with the discussion of emerging applications. We will discuss how these sensors are driving new use cases & trends for developing new package architectures for MEMS applications. The implications of these trends like sensor fusion & integration approach to combine multiple sensors in single package; the trend towards further miniaturization as well new use cases like water proof package technologies etc. will be reviewed in the context of developing new materials & processes as well as managing trade-offs to meet package performance, quality & cost goals.
Ubiquitous Display, The Golden Age of OLED
Zhisheng Li
Senior Researcher in X-Vision Lab - Visionox Technology
Ubiquitous display means display will be everywhere in the future life. During this golden age of display technology, the flexible AMOLED technology will face plenty of opportunities and difficult challenges at the same time. Microled may be another potential candidate for the future display technology.
Wafer Level Packaging and Heterogeneous Integration
Russell Liu
VP Sales & Marketing - China WLCSP
Moore's law has been pushing the industry on the road of scaling to a new height where alternative solutions were needed. In order to achieve both the form-factor and manufacturing cost, IC design companies are looking beyond SOC's for various reasons. In the case of sensors, it might be more cost effective to use different technology nodes for analog and signal processing for example. These different chips could be integrated using today's packaging scaling approaches to realize better performance, design flexibility and lower cost structure. We will probably seeing more designs to integrate processors, signal processors, cache, sensors, photonics, RF, and MEMS for the new generation of IOT devices in the future.
Thank You and Adjourn
Speakers
Farhang Yazdani
President & CEO - BroadPak
John Lee
Sr. Director, Strategic Marketing Greater China Sales & Marketing - Amkor Technology
Dr. Dyi-Chung Hu
CEO - SiPlus
Yaojian Lin
Vice President - JCET
David Wang
Manager Product Application Engineering and Corporate R&D - SPIL
Dongshun Bai, Ph.D.
Deputy Business Development Director of the Wafer-Level Packaging Materials Business Unit - Brewer Science
Kevin Khoo
Marketing Director, Advanced Packaging, LS-SWIFT Division, Global Products Group – KLA Corporation
Chan Pin Chong
Senior Vice President, EA/APMR & Wedge Bonders Business Units - Kulicke & Soffa
Yifan Guo
Vice President of Engineering - ASE Group
Lio Li
Front-End Engineering Manager/ECP Program Manager - AT&S China
Tian TianCheng
Boschman Advanced Packaging Technology
René Betschart
Senior Vice President Besi Products Asia & Besi Singapore - Besi
Romain Fraux
CEO - System Plus Consulting
Yasuhiro Morikawa
Senior Manager of Global Market & Technology Strategy Division - ULVAC
Dr. Pan Zhengang
VP of New Radio Tech. - Unisoc
Bin Fu
Head of Business Development and Marketing China - Bosch Sensortec
Min-hwa Chi
Senior Vice President / Td - Sien (Qindao) Integated Circuit
Debbie Claire Sanchez
FOWLP Equipment Product Manager - Ers Electronic Gmbh
Daping Yao, Ph.D.
Technical Director - NCAP China
Vijay Wakharker
Manager Of Research & Development - Advanced Mems Packaging - TDK InvenSense
Zhisheng Li
Senior Researcher in X-Vision Lab – Visionox Technology
Russell Liu
VP Sales & Marketing - China WLCSP
Thibault Buisson
Chief Operating Officer - Yole Développement
Emilie Jolivet
Division Director Semiconductor & Software - Yole Développement
Santosh Kumar
Principal Analyst And Director Packaging, Assembly & Substrates - Yole Korea
Favier Shoo
Technology and Market Analyst - Yole Développement
Sponsors

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BE Semiconductor Industries N.V. (“Besi”) is a leading supplier of semiconductor assembly equipment for the global semiconductor and electronics industries focusing primarily on the advanced packaging segment of the market. Besi develops leading edge assembly processes and equipment for leadframe, substrate and wafer level packaging applications in a wide range of end-user markets including electronics, mobile internet, cloud infrastructure, computing, automotive, industrial, LED and solar energy. Customers are primarily leading semiconductor manufacturers, assembly subcontractors and electronics and industrial companies. Besi’s ordinary shares are listed on Euronext Amsterdam (symbol: BESI). Its Level 1 ADRs are listed on the OTC markets (symbol: BESIY Nasdaq International Designation) and its headquarters are located in Duiven, the Netherlands. Research and Development is organized in Switzerland, Austria and the Netherlands. Support and production are in Singapore, Malaysia and China.
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The best valued Company which leads the future. Our goal is to be the best valued company leading technology standard. Since HANMI Semiconductor founded the semiconductor equipment industry in 1980, we have grown steadily into a world best Middle-End Semiconductor Equipment Manufacturer & maintain the top position. Through our continued export promotion policy, our high-end technology has been shipping abroad to our more than 280 global customers and this led to more widespread appreciation of its value. Especially, Sawing & Placement System, which was designated as the “World-Class Product’ is recording the first of global market share. Hanmi TSV Dual Stacking TC Bonder has won “2017 iR52 Jang Young-Sil Award”. Hanmi provides distinguished products and services for ‘Customer Satisfaction’. Hanmi won 2016 VLSI Customer Satisfaction Survey The Best Award & 10 Best Award. Also, HANMI has been successful to get original technology with intensive R&D investment and selected as “Advanced Technology Center’ in 2008. Hanmi has 290 R&D Engineers and owns 810 worldwide Intellectual Properties. HANMI Semiconductor is trying to be the best valued company as the pioneer spirit of the first Korean semiconductor equipment manufacturer.
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NAURA Technology Group Co., Ltd. (Hereinafter referred to as NAURA), is a leading enterprise of integrated circuit high-end technological equipment in China. It was formed through a strategic restructuring between Beijing Sevenstar Electronics Co., Ltd. (Hereinafter referred to as Sevenstar Electronics) and Beijing North Microelectronics Co., Ltd. (Hereinafter referred to as NMC). Having inherited years of high-technology research and development strength of Sevenstar Electronics and NMC, NAURA integrated its resources and complemented its advantages with a new futuristic perspective based on technological innovation. The company devotes itself to quickening its strategic transformation to become a part of the new-type manufacturing industry, becoming an international leading product service provider for high-end electronic technological equipment and precision electronic components, to improving the smart-living, and realizing China’s dream of “strengthening a country through intelligence“. NAURA owns four business groups: semiconductor equipment, vacuum equipment, new energy lithium battery equipment and precision components, which provide solutions for semiconductors, new energy resources, new materials as well as other fields. At present, NAURA owns four major industrial manufacturing bases, and its marketing service system covers major countries and regions in Europe, America and Asia. In the future, NAURA will shine in the world arena as a leading firm in high-end electronic technology equipment and precision electronics, strive for further development and lead the way for the future. Furthermore, NAURA will also stick to customer demand-oriented sustainable innovation to promote the progress of industrial technology and bring infinite possibilities for the industry.
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More information: www.kns.com

GIVEAWAYS & BROCHURE SPONSOR
MooreElite is a leading IC design accelerator, providing IC design services, supply chain management, talent services and enterprise services for over 1500 fabless and 500,000 semiconductor professionals. Our mission is “Make IC Design Easy & Efficient”. We are committed to providing ASIC design and Turnkey solutions, from Spec/FPGA/Algorithm to chip delivery, including chip architecture planning, IP selection, front-end design, DFT, digital verification, physical design, layout, tape out, packaging and testing services to help our customer succeed in the market. Since 2012, our team has been serving customers with knowledge of how to get the most out of silicon, offering flexible service models such as Turnkey, NRE, consulting and onsite support. Head-quartered in Shanghai, China, MooreElite has over 230 employees worldwide, with offices in Beijing, Shenzhen, Hefei, Chongqing, Suzhou, Guangzhou, Chengdu, Xi’an, Nanjing, Xiamen, Hsinchu and San Jose.
More information: www.mooreelite.com

LOGO SPONSOR
The SMT Solutions segment within the ASM Pacific Technology Group
The mission of the SMT Solutions segment within the AMS Pacific Technology Group (ASMPT) is to implement and support the smart SMT factory at electronics manufacturers worldwide.
ASM solutions such as SIPLACE placement systems and DEK printing systems support the networking, automation and optimization of central workflows with hardware, software and services that enable electronics manufacturers to transition to the smart SMT factory in stages and enjoy dramatic improvements in productivity, flexibility and quality.
Since maintaining close relationships with customers and partners is a central component of ASM’s strategy, the company has established the SMT Smart Network as a global forum for the active exchange of information between and with smart champions. In addition to being a founding member of the ADAMOS joint venture for the development of an IIoT platform for manufacturing companies, ASM is establishing together with other SMT manufacturers the open HERMES standard as a successor to the SMEMA standard for M2M communication in SMT lines.
For more information about ASM, visit www.asm-smt.com.
ASM Pacific Technology Limited
ASMPT, founded in 1975, is the only company in the world that can offer high-quality equipment for all major steps in the electronics manufacturing process – from carrier for chip interconnection to chip assembly and packaging to SMT. No other supplier offers a comparable range and depth of process expertise.
ASMPT’s Back-end Equipment Business offers a diverse product range from bonding to molding and trim & form to the integration of these activities into complete in-line systems for the microelectronics, semiconductor, photonics, and optoelectronics industries. Its Materials Business provides customers with a variety of leadframes such as etched and stamping as well as advanced packaging materials. ASMPT SMT Solutions develops and sells best-in-class DEK printers for the SMT, semiconductor and solar markets as well as best-in-class SIPLACE SMT placement solutions.
ASMPT is listed in the Hong Kong Stock Exchange since 1989.
For more information about ASM, visit www.asmpacific.com

EXHIBITOR
Bowman is a world-leading manufacturer of precision XRF coating measurement systems, with a robust local service network to support every system, at each customer location, worldwide. Our mission is to support you during every phase of your system’s lifecycle – from system evaluation, selection, and commissioning, through maintenance and modernization. Bowman service partners provide comprehensive, same-day service response for every need; we also work with customers to streamline their testing processes, and to generate the qualitative and quantitative information that’s required, in less time. Our commitment : to deliver support solutions tailored to the needs and quality culture of each individual customer, so that, with each subsequent XRF system purchase, there is no question… that the system will be a Bowman.
More information: www.bowmanxrf.com – www.applytest.com

MEDIA SPONSOR
IC CAFÉ was jointly founded by various experts from the High-Tech chains in 2012. It focuses on ICT fields, mainly in chip and hardware industry. IC CAFÉ offers various business services, such as makerspace service, investment and financing advisory. At present, IC CAFÉ has set up its companies in Nanjing, Shanghai, Beijing, Wuhan, Singapore and some other areas at home and abroad.
Among so many national makerspaces, IC CAFÉ is the organization focuses on IC industry which conferred by Ministry of Science and Technology of China, and it has realized the convergence and share of industry resources by connecting the enterprises from upstream and downstream chains of IC industry.
More information: iccafe.tuweia.cn
Wechat Subscription Number and QR Code : iccafe-sh

MEDIA SPONSOR
GSI Media was established in 2015, with the mission of building and serving the semiconductor community with most valuable industry based contents and services. GSI Media is currently one of China’s top-rated media and community brands, thanks to the high quality of contents and its long term commitment to grow the broad base of community. The business of GSI Media ranges from news reporting, market research, headhunting and finance.
Currently there are 5 Wechat public accounts under the GSI Media umbrella,GSI Media has a total of 300,000 readers from semiconductor industry, owns and manages 100+ Wechat communication group. Until today, GSI Media has influenced millions of professionals from semiconductor industry.

MEDIA SPONSOR
Semiinsights is a professional independent media focused on the semiconductor industry, recognized by semiconductor professionals for its depth, professionalism and integrity, with more than 500,000 subscribers. We are one of the top ranking vertical new media in China.
More information: www.semiinsights.com
Partners

POWERED BY
Founded in 1998, Yole Développement, the “More than Moore” market research & strategy consulting company has grown to become a group of companies providing marketing, technology and strategy consulting, media in addition to corporate finance services. Yole Développement group provides market research, technology analysis, strategy consulting, targeted media, and financial advisory services. We have a global vision and customer base… The “More than Moore” company Yole and its partners System Plus Consulting, Blumorpho, PISEO and KnowMade support industrial companies, investors and R&D organizations worldwide to help them understand markets and follow technology trends to develop their business… Our fields of expertise: MEMS & Sensors – Imaging – Medical Technologies – Compound Semiconductors – RF Electronics – Solid State Lighting – Displays – Photonics – Power Electronics – Batteries & Energy Management – Advanced Packaging – Semiconductor Manufacturing – Software & Computing – Memory and more…
More information: www.yole.fr

HOSTED BY
As an innovation model, National Center for Advanced Packaging Co., Ltd. (NCAP China) was registered in Wuxi New District, China, in September 2012. Supported by Wuxi and Jiangsu government, National Science and Technology Major Project(02 Project) and IC Packaging and Testing Industry Chain Technology Innovation Strategic Alliance, NCAP China, a joint venture with a capital of 234.45 million, is established by ten investors, including the leaders of the IC packaging and testing industry in China (Jiangsu Changjiang Electronics Technology, TongFu Microelectronics, Huatian Technology, Shennan Circuit Company, China Wafer Level CSP, AKM Electronic Technology (Suzhou), Jiangsu CAS Internet-of-things Technology Venture Capital, Shenzhen Fastprint Circuit Tech) and CDB Capital. NCAP’s goal is to establish a national R&D center for advanced packaging and system integration, play a global leading role in the development and commercialization of advanced technologies for microelectronics packaging and system integration, and promote and sustain the technological and commercial advancement of the microelectronics industry in China.
More information: www.ncap-cn.com