EPTC 2021

Tradeshows & Conferences

Online

The 23rd IEEE Electronics Packaging Technology Conference (EPTC2021) is an international event organized by the IEEE RS/EPS/EDS Singapore Chapter and co-sponsored by IEEE Electronics Packaging Society (EPS). It aims to provide a platform to showcase technology innovations and new developments in semiconductor packaging and component technology, from design to manufacturing. It covers diverse areas of electronics packaging technology, including modules, components, materials, equipment technology, assembly, reliability, interconnect design, device and systems packaging, heterogeneous integration, wafer-level packaging, flexible electronics, LED, IoT, 5G, autonomous vehicles, photonics, emerging technologies, 2.5D/3D integration, and smart manufacturing.   

Yole Développement will participate in the following:

Memory Packaging Trends

Emilie Jolivet, Division Director, Semiconductor & Software, Yole Développement
Date coming soon

Memory is a critical market in modern data-centric societies and is driven by important megatrends, including mobility, cloud computing, artificial intelligence (AI), and the internet of things (IoT). All these are fuelling the “data-generation explosion” and are responsible for a robust growth in memory-bit demand.
The memory packaging market follows the same trends that rule the stand-alone memory market and will benefit from the robust growth of memory-bit demand and from the ongoing memory-wafer capacity expansion. Different from the stand-alone memory market that is characterized by strong price volatility, the memory packaging market is less volatile, since most of the business is carried out internally by memory IDMs. In 2020, we estimate that less than 30% of the memory packaging revenue is generated by OSATs.
Memory Packaging in China is a key business opportunity for OSATs: the two rising memory players in China – YMTC (NAND) and CXMT (DRAM) – do not have experience in assembly/packaging and must outsource all their packaging to OSATs. We estimate that the OSATs’ business opportunity related to these Chinese memory players can grow from <$100M in 2020 to ~$1.1B in 2026 (CAGR
20-26 ~55%).
Wirebond is the most common memory packaging technology. It accounts for >99% of NAND packaging revenues and nearly 100% of mobile DRAM (LPDDR). Packaging for PC and server DRAM has been progressively migrating from wirebond to flip chip. The adoption of flip-chip packaging with short interconnects – suitable for low-latency data transfer – will be essential to fully exploit the potential of DDR5 and subsequent DRAM generations.
With the ongoing slowdown of Moore’s Law and the rise of new advanced packaging techniques, back-end processing has gained more and more importance, and several semiconductor companies are now leveraging on it – rather than on the front-end – to improve the performance, the compactness and the number of functionalities of their IC products. Heterogenous integration techniques (e.g., TSMC’s SoIC) and chiplet architectures enabled by novel stacking/bonding approaches have become the must-follow approaches to increase the performance of computing systems through a tight integration of logic and memory building blocks.
Yole Développement will give a holistic view of the memory packaging industry in this presentation.

Technology and Market Briefing on Semiconductor Packaging

Favier Shoo, Team Lead Analyst, Packaging, Yole Développement
On-demand

Fueled by digital end-system demands and technological innovation, Advanced Packaging technology options are increasingly rich and ground-breaking. Performance/power improvements at escalating cost associated with Moore’s Law scaling had triggered semiconductor industry to strategize system-level scaling with Advanced Packaging solutions instead of purely scaling FE advanced nodes. The industry is now diligently using advanced packaging technologies to put multiple advanced and/or mature chips in a single package. Together with 3D packaging this extends Moore’s Law at system-level. Times have changed. The total IC packaging market was worth $68B in 2020. Advanced Packaging was worth $30B and is expected to grow at CAGR2020-2026 of 8% to reach $48.2B in 2026. At the same time, traditional packaging market will grow at CAGR2020-2026 of 4.3% and total packaging market will grow at CAGR2020-2026 of 6% to $47.9B and $96.1B, respectively. Compared to traditional packaging which will grow at 3.2% CAGR2014-2026, Advanced Packaging  will grow more than 2 times quicker, with its CAGR2014-2026 of 7.5%. Two Advanced Packaging roadmaps are foreseen – scaling (going to sub10 nm nodes) and functional (staying above 20nm nodes). The semiconductor manufacturing supply chain is undergoing change at various levels. In order to expand the business and explore new areas, players in semiconductor supply chains are moving to different business models. Among them, the most dynamic is the Advanced Packaging business.

Cet article vous a plu ?

Partagez-le sur vos réseaux sociaux