Power and RF Packaging Virtual Forums – presented by Yole Développement and CITC

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Packaging technologies are expanding the boundaries of RF and power applications

Yole Développement, a renowned market research company, and CITC, an innovation center with extensive technical and market experience, invite you to take part in two collaborative online forums covering power packaging and RF packaging. Challenges have emerged for both applications concerning the integration of devices and systems – and to ensure these applications’ continued evolution and activity development, packaging is the strategic answer.

With increased functionalities, companies must refine their ability to integrate more and more components on the same die while proposing an exceptionally reliable final product.
Save the date in your agenda today and let’s meet online on November 24 and December 1, 2020!

Speakers have been confirmed – Discover who they are for each forum below!

POWER PACKAGING VIRTUAL FORUM
Tuesday November 24th, 2020 – 2:00PM – 5:00PM CET

How packaging energizes the needs of power applications

Power electronics plays a major role in today’s fast-paced world. Its key driving factors include electrical power-conversion optimization and expansion, driven by electrification trends in transportation, CO2 emission reduction goals, the development of clean electricity sources, and industrialization.

Choosing the right packaging solution is obviously key for power-related applications where reliability and safety play a major role.

Due to stronger requirements, a higher added-value for customers, and a greater desire for competitive differentiation, most innovative packaging solutions focus on power modules and integrated devices like system-on-chip (SoC) and system-in-package (SiP). Whereas in the past packaging needs were driven by industrial applications, today they are increasingly driven by electric and hybrid electric vehicles (EV/HEV). Hence, power module packaging solutions are moving towards high-performance materials and a reduction in the number of layers, size, and interfaces – all while conserving electrical, thermal, and mechanical characteristics.

Confirmed speakers:

Shijo Nagao, Associate Professor – Osaka University / Yamato Scientific
Ronald Eisele, Professor – Fachhochschule Kiel, Institut für Mechatronik
Braham Ferreira, Professor in Power Electronics, Electrical Engineering, Mathematics & Computer Science – University of Twente
Christoph F. Bayer, Group Manager Packaging for Power Modules – Fraunhofer Institute for Integrated Systems and Device Technology IISB
Shaun Bowers, VP, Mainsteam Advanced Package Integration – Amkor Technology
Alexander Streibel, Senior Application Engineer – Danfoss

RF PACKAGING VIRTUAL FORUM
Tuesday December 1st, 2020 – 2:00PM – 5:00PM CET

New market demands create a strong connection between packaging & RF

RF electronics is currently experiencing strong growth, driven mostly by 5G requirements and connected devices. Examples of RF electronics include connectivity modules in smartphones and smartwatches, and radar for ADAS vehicles. These are growing systems requiring innovative packaging solutions which simultaneously address specifications for cost, form factor, and performance. Other challenges related to signal integrity and low power consumption are starting to be addressed by the industry, with new solutions on the way.

Innovation is needed for the design and materials used, thus pushing the supply chain to explore new developments and more complex business models. The diversity of RF components (power amplifier, filters, switches, antennas, etc.) requires the use of several levels of integration as well as different packaging platforms and interconnects (TSV, wirebond, etc.).

Confirmed speakers:

Jussi Säily, Senior Scientist – VTT Technical Research Centre of Finland
Hanwen Zhang, Global Product Manager of Advanced Packaging Solder Materials – Heraeus
Mario Ibrahim, Senior Market & Technology Analyst – AT&S
Michael Gallagher, R&D Fellow – Advanced Packaging Technologies – DuPont Electronics and Imaging
Marco Spirito, Associate Professor – TU Delft
Ram Trichur, Global Market Segment Head, Semiconductor Packaging Materials – Henkel

SPONSORSHIP OPPORTUNITIES

Our Program

NOVEMBER 24, 2020

1:00 pm - 2:00 pm

Registration

2:00 pm - 2:26 pm

Welcome and introduction

2:06 am - 2:16 am

CITC presentation

2:16 pm - 2:26 pm

Yole Développement presentation

2:26 pm - 2:48 pm

Speaker 1: Osaka University / Yamato Scientific Co., Ltd.

Evaluating thermal properties of metalized ceramic substrates for power module packaging

Mr. Nagao Shijo

Associate Professor

In recent power module packaging, thermal management attracts various researchers and engineers who design high-power-density power devices. Even with utilizing wide-bandgap semiconductors like SiC and GaN exhibiting excellent conversion efficiency, increasing heat density is not negligible due to requiring miniaturization. Those semiconductor device chips are usually die-attached to a printed metal circuits or metalized ceramic substrate. The latter is advantageous for high power applications because of the higher breakdown voltage and higher heat conductivity. In such a case, most of the heat dissipates through the path from the heat-generating chip, die-attach material, Cu circuit layer of a metalized ceramic substrate, to finally heat sink either water- or air-cooled. The die attach material and the ceramic substrate that takes the role of insulation contribute high heat resistance, so that appropriate thermal performance evaluation and a fine selection of these materials are the keys of module design. Various types of metalized ceramic substrate produced with AMB (active metal bonding), DBC (direct bonded Cu, or DBA (direct bonded Al), e.g., Cu/Si3N4/Cu, Cu/AlN/Cu, or Al/Al2O3/Al. The measurement of the actual thermal properties of the materials combination with die-attach technologies. Therefore, we propose a standard thermal property evaluation method of a die-attached metalized ceramic substrate. ISO TC206 committee has been reviewing our proposal for international standardization since this spring. The proposed method essentially depends on a newly developed SiC micro heater chip that simulates a real power device like a SiC MOSFET generating high heat of 1 kW/cm2 at maximum. The size and pattern of metalized ceramic substrates are regulated, though combined with any types of die-attache material. Our method determines the thermal resistance in the resolution of σ２ << 0.01 K/W for several individual trials on the same sample because of the optimized geometric and loading conditions. Our method has also extended to power cycle testing with monitoring changing heat resistance. We would discuss the insight of the measurement set-ups and the results of power cycling tests.

2:48 pm - 3:10 pm

Speaker 2: Fachhochschule Kiel, Institut für Mechatronik

Inorganic encapsulation of power ribbons and wire bonds

Mr. Ronald Eisele

Professor

In this investigation the thermal optimization of power electronic contacts by a ceramic composite compared to a conventional polymer encapsulation was quantitatively determined. A Cu ribbon (1.5mm/200µm), an Al ribbon (1mm/100µm) and an Al wire (400µm), which were not subject to external thermal stress by a semiconductor, were examined. The quantification of the increase in current carrying capacity and power density was determined metrologically and by FEM simulations. The simulation model was subjected to an internal model correction and then verified by precise measurements with an infrared camera in air. Thus the comparative measurements with miniature thermocouples in the encapsulation could be checked with the valid theoretical results of the simulation model. With a correction of the systematic sensor error, the measurements provide valid results. Thus, the increase in ampacity for the Cu ribbon could be quantified at 41%, for the Al ribbon at 119% and for the Al wire at 97%. The increase in power density is 30% for Cu ribbon, 374% for Al ribbon and 366% for Al wire. Especially Al bonds of small cross section benefit from ceramic encapsulation. For the Cu ribbon, the corrosion process by scaling in high performance thermal operation was investigated to determine a thermal upper limit for the operation of the Cu ribbon in the ceramic encapsulation without scaling. For this purpose the Cu ribbon was thermally loaded with a direct current. The corrosion kinetics were determined indirectly via temperature and voltage. Thus the corrosion process could be observed at over 350°C. The chemical detection of the oxide layer was carried out by a SEM analysis. The thermal upper limit is at least 250°C. This corresponds to the predicted junction temperatures of future WBG semiconductor generations. A single sample reached 302°C. At the boundary of Cu ribbon and ceramic encapsulation a cover layer of and (filler of the encapsulation) could be detected, which seems to have a passivating effect in this temperature range.

3:10 pm - 3:33 pm

Speaker 3: University of Twente

Fabrication plant for Power Electronic System In Package

Mr. Braham Ferreira

Professor in Power Electronics, Electrical Engineering, Mathematics & Computer Science

A continuous supply of energy is of vital importance of our modern society and an increasing part of that energy supply is transferred from fossil to electrical energy. Hence electrical power systems will play an increasing vital role in our energy systems. Future miniaturized GaN based power electronic converters will not only rely on heterogeneous integration at chip level (SiP), but also requires co-designed advanced PCB technologies to solve the thermal, RF and reliability issues associated further miniaturization. Such high level system optimization involves a complex three-dimensional interplay between various organic materials and metals, integrated LCTs and clever high frequency circuit and SiP design. Specifically the electromagnetic integration of the passive components such as the resonant tank, low pass filter, high frequency transformer and EMI filters, with different scaling rules compared with micro- and power electronics requires special attention. To address these challenges The Shenzhen-Twente Power Electronics group, embedded in the Shenzhen Institute of Wide Bandgap Semiconductors (WinS) in Shenzhen, is developing a heterogeneous fabrication process for GaN power electronics on organic substrates.

3:33 pm - 3:39 pm

Short break

3:39 pm - 4:01 pm

Speaker 4: Fraunhofer Institute for Integrated Systems and Device Technology IISB

Future Packaging Technologies in Power Electronic Modules

Mr. Christoph F. Bayer

Group Manager Packaging for Power Modules

This paper summarizes power electronics packaging trends and technologies that were identified at the Fraunhofer IISB as promising in future. Due to upcoming demands including further integration, minimization, modularization, high temperature and high voltage capability, listed packaging topics are recently addressed and researched. Besides a deeper insight into three main topics, high switching speed by RC-snubber devices and high current copper projection welding are presented. Main topics are ceramic embedding by subtractive manufacturing processes for harsh environments and best semiconductor electrical interconnect, selective sintering of power electronic devices on organic circuit carriers for higher process flexibility, higher powers and long lifetime, as well as direct bonding without sinter or solder material as a novel interconnection technology in power electronics.

4:01 pm - 4:23 pm

Speaker 5: Amkor Technology

Chip Scale Power Transistor Packaging

Mr. Shaun Bowers

VP, Mainstream Advanced Package Integration

Power packaging technologies are split between discrete and integrated solutions, using a wide variety of form factors and sizes. Applications in power management, delivery, conversion and switching are all ripe for innovation. Recent advancements in packaging allow for size reduction with enhanced electrical performance and integration. This presentation will explore power packaging technologies in use today and introduce Amkor’s new PowerCSP™ chip scale package family for both discrete and integrated power.

4:23 pm - 4:47 pm

Speaker 6: Danfoss

New Packaging Technologies boost drive train efficiency

Mr. Alexander Streibel

Senior Application Engineer

Power electronics packaging technologies are strongly driven by automotive applications. This speech will provide insights into how advanced power module technologies can boost the efficiency for the next generation of electric drive trains. An overview of OEM requirements will be given that challenge the power semiconductor landscape as well as the materials, the bonding and joining technologies, the packaging and cooling concepts of power modules. The power module of tomorrow must match with innovative inverter designs to enable high-efficiency solutions. The new Danfoss DCM1000 technology family is a good showcase platform how the above-mentioned requirements can be fulfilled.

4:47 pm - 4:52 pm

Thanking, summarize and provide follow up information

DECEMBER 1, 2020

1:00 pm - 2:00 pm

Registration

2:00 pm - 2:26 pm

Welcome and introduction

2:06 am - 2:16 am

CITC presentation

2:16 pm - 2:26 pm

Yole Développement presentation

2:26 pm - 2:48 pm

Speaker 1: VTT Technical Research Centre of Finland

Design of advanced mm-wave phased arrays

Jussi Säily

Senior Scientist

In order to take advantage of the full capability of 5G millimetre wave systems beam forming is required on both sides of the radio link. Base station side can have complex high performance phased antenna arrays while the mobile devices feature simpler beam steering or beam switching antennas. MIMO capable antenna arrays have several independent antenna panels which can operate independent beams inside the same antenna sector.The main advantage of phased array antennas is spatial power combining which makes possible very high equivalent isotropic radiated power (EIRP). A phased array antenna can point narrow antenna beams toward users thus reducing stray radiation and increasing signal to noise ratio in the radio link. Nulls in radiation pattern can also be generated toward possible interferers.Typically a phased array antenna consists of several hundreds of antenna elements each having their own power amplifier (PA) and low noise amplifier (LNA). This requires high component integration level into so-called core chips having four or more antenna connections. Commonly used IC technologies are CMOS and SiGe. The antenna element size at millimetre wavelengths (>30 GHz) is small thus enabling large scale antenna arrays and separate TX and RX arrays. Components and antenna elements are typically integrated together on a low-loss printed circuit board (PCB). Thermal dissipation of the antenna array can be hundreds of watts so advanced thermal management methods must be applied.In this presentation the basic concepts and some 5G and beyond phased antenna array examples (both commercial and research) are discussed for different frequencies between 28 - 150 GHz.VTT has decades long experience in developing millimetre wave integrated circuits (MMIC), printed circuit board technology and low temperature co-fired ceramic (LTCC) substrate manufacturing, antennas and measurement technologies.

2:48 pm - 3:10 pm

Speaker 2: Heraeus

Challenges of Solder Joint Reliability in RF SiP Modules

Hanwen Zhang

Global Product Manager of Advanced Packaging Solder Materials

With the rise of 5G, the advanced packaging activities of RF Front-End modules is growing tremendously both in volume and complexity. RFFE modules enabled by System-in-Package (SiP) technologies require the application of solder paste to form numerous solder joints in a single package. Any solder joint failure can result in failure of the module. In this presentation, the various challenges of solder joint reliability in RF SiPs will be reviewed in detail. The key factors to mitigate or overcome these challenges, including stencil design, flux chemistry types, solder powder quality and all-in-one printing process of solder paste will be discussed.

3:10 pm - 3:33 pm

Speaker 3: AT&S

5G is a Megatrend no one is questioning that!

Mario Ibrahim

Senior Market & Technology Analyst

Despite a slight slowdown in its implementation due both Covid-19 pandemic and the China/USA trade war, 5G is continuously pushing new RF technology developments.Better thermal management, higher performances and miniaturization are some of the key parameters needed for a 5G RF component. This implies more complex RF modules with higher die integration, higher substrate complexity (increased layer count, finer line/space, usage of advanced processes) combined with suitable materials.We at AT&S are on the forefront of answering the 5G RF devices challenges. Solutions using embedded die technology or novel substrate structures combined with advanced processes (mSAP) are possible, answering the need of 5GmmWave AiP and other RF devices.Join me to discuss RF devices substrate and packaging, debate on the RF challenges, brainstorm on AT&S’ solutions and imagine the future of RF components.

3:33 pm - 3:39 pm

Short break

3:39 pm - 4:01 pm

Speaker 4: DuPont Electronics and Imaging

Dielectric Materials for High Speed and High Frequency Applications

Michael Gallagher

R&D Fellow – Advanced Packaging Technologies

AI, Autonomous driving, 5G, IoT and smart connectivity have increased the need for high data transfer rates and greater bandwidth which requires a multigenerational connectivity network over the next few decades. The ubiquitous demand for data and connectivity has created needs for materials with advanced properties to deliver high performance in this expanding ecosystem. Designers faced with new demands arising from frequencies of 20 Gigahertz and beyond are challenged by miniaturization, shorter development cycle times and need for cost effective solutions. Critical areas requiring new material innovations include high speed digital, high frequency applications, thermal management, shielding needs and power optimization.To meet these challenges, DuPont offers a wide range of customizable materials including low loss dielectric resins and laminates, conductor metallurgies, ceramics, and materials for heat dissipation and power optimization. Our solutions for high speed and high frequency systems are widely used in applications for mobile, radar, telecommunications, satellite technology, consumer, medical and a host of others where a high level of reliability, efficiency and performance are critical. The materials to be discussed in this session include • Low Temperature Co-Fired Ceramics (LTCC) materials • Liquid and dry film low loss dielectrics • Flexible materials for 5G

4:01 pm - 4:23 pm

Speaker 5: TU Delft

Marco Spirito

Associate Professor

4:23 pm - 4:47 pm

Speaker 6: Henkel

Critical Materials for 5G and RF Semiconductor Packaging

Ram Trichur

Global Market Segment Head, Semiconductor Packaging Materials

The market for 5G infrastructure and mobile devices is set to increase rapidly in the next few years. Several major communication companies have set up their infrastructure in major cities or hubs to deliver 5G data to their customers both in sub-6GHz range and in mmWave range. All major mobile handset manufacturers also have released their higher-end smartphones with 5G compatibility. After this initial roll-out, the deployment rate will be increased to include other global tier-one, tier-two cities, and suburban areas.These new 5G elements in the infrastructure side and handset side operate at much higher frequencies than previous 4G or LTE formats leading to several implications in IC packaging. Some examples are, firstly, the antenna size can now be reduced to the semiconductor package size, and the antenna arrays can be integrated into the substrate or the IC package itself. Secondly, to have more integration on the RF front-end chip, esp. with the increase in the number of power amplifiers, filters, and switches required to field multiple frequency bands which leads to larger thermal dissipation needs. These complex IC packaging scenarios for antenna integration, multiple IC integration, and thermal dissipation requires innovation in materials, process, packaging technology, and system architecture.In this talk, I will present key innovations in three materials for RF front end packaging. First, I will cover the key characteristics of hybrid sintering materials that enable high thermal conductivity in semiconductor die attach. Then I will introduce the liquid compression molding material that enables wafer-level integration and packaging of RF ICs. Finally, I will present innovative materials for compartmental and conformal shielding of an IC package to avoid electromagnetic interference between components at the IC package level.

4:47 pm - 4:52 pm

Thanking, summarize and provide follow up information

Speakers of Power and RF Packaging Forum

Shijo Nagao
Associate Professor - Osaka University / Yamato Scientific - Power Forum
Ronald Eisele
Professor - University of Applied Science, Fachhochschule Kiel - Power Forum
Braham Ferreira
Professor in Power Electronics, Electrical Engineering, Mathematics & Computer Science - University of Twente - Power Forum
Christoph F. Bayer
Group Manager Packaging for Power Modules - Fraunhofer Institute for Integrated Systems and Device Technology IISB - Power Forum
Shaun Bowers
VP, Mainstream Advanced Package Integration - Amkor Technology - Power Forum
Alexander Streibel
Senior Application Engineer - Danfoss - Power Forum
Jussi Säily
Senior Scientist, VTT Technical Research Centre of Finland - RF Forum
Hanwen Zhang
Global Product Manager of Advanced Packaging Solder Materials, Heraeus - RF Forum
Mario Ibrahim
Senior Market & Technology Analyst, AT&S - RF Forum
Michael Gallagher
R&D Fellow, DuPont Electronics and Imaging - RF Forum
Marco Spirito
Associate Professor, TU Delft - RF Forum
Ram Trichur
Global Market Segment Head, Semiconductor Packaging Materials, Henkel - RF Forum

Co-organized by

Yole Développement provides market research, technology analysis, strategy consulting, targeted media, and financial advisory services.

With a strong focus on emerging applications using silicon and/or micro manufacturing since 1998, Yole Développement has expanded to include more than 80 collaborators worldwide covering Photonics – Lighting – Imaging – Sensing & Actuating – Display – RF Devices & Technologies – Compound Semiconductors & Emerging Materials – Power Electronics – Batteries & Energy Management – Semiconductor Packaging and Substrates – Semiconductor Manufacturing – Memory – Computing and Software.

The market research, technology and strategy consulting company Yole Développement, along with its partners System Plus Consulting, Blumorpho and PISEO – all part of the Yole Group of Companies-, support industrial companies, investors and R&D organizations worldwide to follow technology trends to grow their business and help them understand the 6 specific markets.

More info: www.yole.fr

CITC is a non-profit innovation center that specializes in heterogeneous integration and advanced packaging technology. It is a place where companies, research and educational institutes work together on bridging the gap from academics to industry and create new and better solutions. Therefore we offer access to innovation, infrastructure and education.

Access to Innovation
Organizing and running innovation programs in the field of chip packaging and integration technology.

Access to Infrastructure
Providing access to lab infrastructure as one of CITC’s key capabilities.

Access to Education
Sharing knowledge about integrated chip technology and its applications.

More info: www.citc.org

#Packaging #Power Electronics #RF Devices And Technology

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