Semicon Southeast Asia 2019

Tradeshows & Conferences

Kuala Lumpur, Malaysia

Yole Développement invites you to join us at Semicon SouthEast Asia.

While Southeast Asia is rising up fast as a world-class electronics manufacturing hub with end-to-end R&D capabilities – SEMICON Southeast Asia has become an important exposition for the electronics industry in Southeast Asia. The show connects the decision makers from the industry, demonstrates the most advanced products and brings in the most up-to-date market and technology trends. Bringing solutions to industry challenges that can best be addressed at the event!

Yole Développement will participate in the following:

“Market Trends in Advanced Packaging”

On May 9th, 2019 at 12:00PM
Favier Shoo, Technology & Market Analyst, Package Assembly and Substrate at Yole Développement

Abstract: Semiconductor market driver is turning from mobile to more scattered applications in the future – IoT (and IIoT), Automotive, 5G, AR/VR, AI. In this digital new age, advanced nodes do not bring the desired cost benefit anymore and R&D investments in new lithography solutions and devices below 10nm nodes are rising substantially. Hence, advanced packaging represents an opportunity to increase product value (higher performance at lower cost) offering advantages down both the scaling and functional roadmaps. Advanced Packaging stands at $25.7B in 2017, continues to raise share in total packaging from 38% (2014) to 41% (2017) with 47% by 2023. Fan-Out, Embedded Die in substrate and TSV platform with highest growths – revenue CAGRs 2017-2023 of 15%, 22% and 29%, respectively. Fan-Out continues to eat market share from the biggest advanced packaging platform, Flip Chip. Other advanced lead frame (e.g. fcQFN) and alternative redistribution technologies (e.g. MIS) have the potential to compete with advanced packaging and gain market share in the lower ends. Two advanced packaging roadmaps are foreseen – scaling (going to sub10 nm nodes) and functional (staying above 20nm nodes). Both roadmaps hold more multi-die heterogeneous integration (SiP) and higher levels of package customization in the future.
3 competitive areas are present and will continue to develop – PCB vs. substrate, substrate vs. Fan-Out, Fan-Out vs. 2.5D/3D. Primary innovation in advanced packaging: decreasing Cu pillar pitch, RDL/substrate development for L/S <10 um (thin film RDL, SAP, Cu damascene RDL and hybrids thereof), further TSV integration (2.5D/3D and MEMS/CIS). Foundries joined, PCB/Substrate suppliers and EMS also joining (advanced) package manufacturing. Intel remains biggest packaging house with TSMC in TOP 10 packaging houses and rising. How difficult is it for OSATs to challenge TSMC high-end domain? This presentation will describe the market dynamics. It will also explain the different solutions and challenges that the industry will have to face.

“Fan-Out Packaging”

on May 8th, 2019 at 1:55PM
Favier Shoo, Technology & Market Analyst, Package Assembly and Substrate at Yole Développement

Abstract: Currently, all key OSAT/foundry/IDaM players have Fan-Out packaging solutions in the market. Fan-Out packaging’s key benefit is the ability to integrate dies together flexibly, and at thinner dimensions. In a mega-trends-driven era, Fan-Out platforms are increasingly viewed as one of the top options amongst leading package technologies.
Fan-Out packaging market value is expected to grow at a 19% CAGR from 2019 – 2024, reaching a market size of $3.8B. Core FO market confirmed its stability, with significant new entrants joining via FOPLP. Although existing FOWLP players has long history of established qualifications, mid-end devices may be too costly for FOWLP players. PTI has invested, developed and started LVM FOPLP production for MediaTek. FOPLP players will emerge as a cost-effective option in core market. In HD FO, TSMC has extended its leadership even further by rolling out inFO-oS for HPCs application. Exciting developments are underway with inFO-AiP for mmWave application and inFO-MS for Server application. TSMC’s aggressive roadmap to go sub-microns in RDL L/S may create new market segment, UHD FO (Ultra HD FO). Furthermore, SEMCO has achieved a new milestone by enabling FOPLP for APE+PMIC in Samsung Galaxy smartwatch. Although this is still considered Core FO in terms of I/O density, it will not be long before SEMCO goes high-end to challenge TSMC for Apple’s APE business.
Key fabless players like Qualcomm and MediaTek will continue to push packaging houses for Fan-Out solutions at lower cost, especially in higher-end devices. Is PTI the only potential option for achieving this, and in the process could reach a new milestone with high-end memory Fan-Out packaging? Will Fan-Out packaging continue to cannibalize and put flip-chip, advanced substrate, and interposer manufacturers out of business? Fan-Out can displace 2.5D interposers with fine L/S Fan-Out packaging on substrate. It can also displace flip-chip and advanced substrate. Such is the potential of Fan-Out packaging technology.