SYNAPS 2020 – Symposium by Yole Développement and NCAP on Advanced Packaging for Semiconductors

Yole Events

Wuxi, China & Online

In these uncertain times, Yole Développement and NCAP are working together to run the symposium as scheduled while guaranteeing health and safety of our participants and an international quality event. Thereby, we adapted the format of our event for this year: in addition to the conference hold onsite in Wuxi, on-demand presentations will be available online for all the attendees who cannot join on-site. In addition, this year, NCAP Open Day will be combined to SYNAPS. We believe that this solution will allow everyone to stay connected with the worldwide packaging industry anyway.

Also, please note that we had to shorten the live date from 2 to 1 day, on September 15th, 2020 and moved to Wuxi, instead of Suzhou.

SYNAPS is happy to be co-hosted with the 7^th NCAP Open Day.

We look forward to conference’s great success during this special time of year.

ADVANCED PACKAGING
IS EVERYONE’S BUSINESS!

REGISTRATION

We invite you to join the Symposium by Yole Développement and NCAP on Advanced Packaging Semiconductors, 2020 edition! For its 6^th edition, the event has been renamed for:

SYNAPS
=
Symposium by Yole Développement and NCAP on Advanced Packaging Semiconductors

One year has passed since the latest successful edition. NCAP and Yole Développement are now back with an exciting 2020 program for you in Wuxi, China, this year.

As of, the agenda will be a powerful mix of key sessions related to the industry evolution and technical innovations and effective network times for people who will get the chance to join us on-site. By combining their technical and market expertise, both partners invite you during one exceptionnal day to gain an in-depth understanding of the advanced packaging industry evolution.

Advanced packaging processes are at the crossroad of all semiconductor manufacturing process steps today. For the overall semiconductor companies, advanced packaging is strategic to answer to the industry evolution and ensure the development of their activities. With more and more functionalities, companies have to manage their ability to integrate more and more components on a same die and propose a final product with a high reliability level.

At SYNAPS, 2020 edition, NCAP and Yole Développement invite you to dive deep into the advanced packaging technologies, understand the latest innovations and discover new business opportunities.

Save the date in your agenda right now and let us meet in Wuxi, China on September 15, 2020 !

TECHNICAL COMMITTEE

Yole Développement and National Center for Advanced Packaging (NCAP China) decided to create and form the 1st Symposium Technical Committee. The Symposium Technical Committee is a 6-member group that takes the leadership role in setting and driving the conference’s content, working together with the Organizing Committee. Our Committee is responsible for ensuring a well-balanced, high quality conference program and is composed of a diverse set of senior industry experts:

Santosh Kumar
Principal Analyst & Director Packaging, Assembly & Substrates, Yole Korea

Dr. Peng Sun
Director of Technology Division, National Center for Advanced Packaging, NCAP China

Farhang Yazdani
President and CEO,
BroadPak Corporation

Ram Trichur
Global Head of semiconductor packaging market segment, Henkel

Amy Leong
Chief Marketing Officer and Senior Vice President of Mergers and Acquisitions, FormFactor

Yifan Guo
VP of Engineering, ASE Group

SPONSORSHIP OPPORTUNITIES

LOCATION AND KEY INFORMATION

LOCATION

Hôtel Pullman Wuxi New Lake

No 30 Hefeng Road
Xinwu District
214135
Wuxi, China

UPCOMING DATES

Call for paper submission: from November 11, 2019 to May 8, 2020
Registration opening : June 17, 2020
Author notification: July 2, 2020
Program reveiled: July 9, 2020
Symposium dates: September 15, 2020

CONTACT

Need more information? Please contact Fanny: fanny.vitrey@yole.fr

Invitation letter

2 offers to suit your needs

PREVIOUS EDITION

Agenda

Septembre 15, 2020

8:00 am - 9:00 am

Registration

9:00 am - 9:10 am

Welcome and Introduction

9:10 am - 10:20 am

Session 1 - (1/2) - Embedded Technologies and System in Package

9:10 am - 9:30 am

Keynote: Low Cost Solution for 2.5D using Fan-Out Embedded Bridge - ONLINE

C. Key Chung, PhD

Senior Director of Advanced Package R&D - SPIL

With transistor scaling reaching both physical and economic barriers, transistor performance and cost have been increasingly lagging behind the historical Moore’s Law trajectory. However, demand for silicon remains incessant with the growth of internet traffic, artificial intelligence, autonomous driving, and big data. Development of electronic devices metaphor to high-density package integration. What the electronic industries do is to break down a large die to a chiplet-based devices for improving yield and lower the total cost. Chiplet package become a key technology to continue Moore’s law. With the intensive researches, multiple chiplet packages are evolved such as multi chips on Si interposer using TSV (2.5D), die to die stack on each other (3D), Fan-Out Multi Chip Module (FOMCM), and EMIB (Embedded Multi-Die Interconnect Bridge). These packages are developed for the server, high performance computing, router, and switcher markets.In this speech, we are introducing a scalable chiplet package technology, namely Fan-Out Embedded Bridge (FOEB). The demonstration of FOEB test vehicle integrates chips by 1 ASIC die and 4 memory dies (1+4) with 4 embedded bridge dies on mold-based interposer, 3 layers of RDL are presented. By comparing packages using FOMCM and 2.5D to fabricate. FOEB package has much lower warpage and 2x lower stress value as compare to 2.5D. But similar to FOMCM. Owing to this reason, the FOEB chiplet package were tested 2x longer temperature cycle with condition-G without single failure as compared to 2.5D. This chiplet allows us to scale the package to much higher I/O density, finer L/S, higher RDL layers, and number of dies that can be integrated into one single chip module.

9:30 am - 9:50 am

Reliability Issues in Advanced Packaging - ONLY ON-SITE

Hongwen He, Ph.D.

Responsible for collaboration plans with colleges and industry - HiSilicon

With the CMOS process node scales down, the advanced packaging technology will face much more challenges and opportunities. The packaging type and size become more complex, diverse and larger, leading to the interconnect density and warpage issues increase seriously. In this presentation, some typical reliability problems in advanced packaging are introduced, such as TIM de lamination, RDL crack, TSV pumping, EM reliability, and so on. The failure mechanism is described according to every single case.

9:50 am - 10:05 am

Meeting the challenges of Large Panel, high density placement in Embedded Die SIP packaging - ONLINE

Sylvester Demmel

Senior Product Manager for SIPLACE Advanced Packaging - ASM Assembly Systems

Miniturisation and modularization, two major trends in Semiconductor packaging continues to be the main driving force to meet the need of a new generation of devices stemming from the introduction of 5G, Internet of Things, and other mobile devices. Advanced packaging technologies, such as embedded dies and fan-out packages, have emerged as the solution to meet the requirement for greater flexibility, faster time to market, and lower costs. This can be processed in large panels that incorporates embedded devices, both passives and active dies. With embedded Die in organic substrate, which can be quickly adapt from existing substrate manufacturing technologies and its electrical benefits, providing a highly scalable and low-cost solution.Many embedded die packages today are assembled with either passives or single die. With the expected growth for modules and the drive for higher performance and increasing functionality within thinner form factors, the trend will be towards multi-dies, or combination of dies and passive in embedded SIP solutions. This increases the complexity and challenge for pick and place equipment in handling large, thin substrate and placing large number of different types of dies and passives into confined spaces.This presentation examines these twin challenges, and the work that ASM has done in partnership with end users, on addressing them using a combination of software implementation, Panel handling and support system, and carrier designs.

10:05 am - 10:20 am

Panel level sputter tool for High Volume Manufacturing (HVM) - ONLINE

Ewald Strolz

Head of Process Development / BU Advanced Packaging - Evatec

Panel level packaging is driven primarily by FOPLP as the next technology after FOWLP to increase productivity and reduce cost by increased substrate size. However, as the line space shrinks further also for organic IC-substrates, conventional large area IC-substrate manufacturing processes (PCB manufacturing technologies) also need to be substituted by advanced technologies such as PVD metallization and sputter etch preclean.As IC-substrate manufacturing and FOPLP consequently use the same technologies already well established and proven for WLP, it makes good sense to develop a process system suitable for both FOPLP & organic laminated substrates.For IC-substrates often organic laminated build-up films with mineral fillers are used. A via descum process is typically required for such substrates after the laser drill step. The descum process needs to be tuned to etch both the organic material and the mineral fillers component of the laminate in a well balanced way and is usually performed by reactive Ion etch (RIE). Ideally it should be integrated on the same sputter tool where other processes are needed (Degas, sputter etch preclean & PVD).A major challenge is the processing of large scale panels which often show a high warpage or sag requiring special handling for reliable transfer and processing. The presentation will explain the key features of a panel level PVD cluster type tool, and describe how the key requirements are fulfilled and supported for both FOPLP and organic substrates for panel sizes up to 650x650mm.

10:20 am - 10:50 am

Coffee break - Networking time

10:50 am - 11:10 am

Session 1 - (2/2) - Embedded Technologies and System in Package

10:50 am - 11:10 am

Keynote: Overview of the Latest PVD Developments for High Density FOWLP - ONLINE

David Butler

EVP & General Manager - SPTS Technologies

To address the needs of high performance computing, high density fan-out wafer level packaging (FOWLP) technology is an increasingly popular and cost-effective solution for obtaining a high level of device integration with a greater number of I/O contacts, in a small package. To increase data bandwidth, RDL line/space geometries are rapidly moving towards sub-micron dimensions. With smaller dimensions, reducing Rc becomes more critical, and challenges in reliability and yield of the various wafer processing technologies becomes a key factor in fan-out’s continuing adoption for these demanding applications.This presentation will discuss solutions for optimizing yield and productivity during physical vapor deposition (PVD) of under-bump and redistribution metal layers. The challenges in PVD processing of FOWLP are varied, such as contamination, particles and wafer warpage. The latest PVD hardware specifically designed for BEOL processing has all the necessary features a UBM/RDL customer requires for this application, such as specialized pre-clean technology and in-situ co-pasting hardware designed to reduce contamination and increase uptime, and multi-wafer degas technology to significantly improve wafer throughput and lower Rc.

11:10 am - 11:30 am

Advanced Packaging Substrate in NCAP - ON-SITE

Qidong Wang

Director of R&D Department - NCAP

IC Substrate has been evolving to meet the demands of upcoming large sized IC, SiP and further Heterogeneous Integration. The state-of-the-art research and development activities in NCAP on Advanced Substrate will be overviewed and with some thoughts discussed.

11:30 am - 12:10 pm

Session 2 - Memory Packaging

11:30 am - 11:50 am

Advanced Assembly Technology for Memory Product - ON-SITE

Shen, Guoqiang

JSCC WB GROUP R&D CENTER AND ENGINEERING TEAM MANAGER - JCET

Memory Markets & Applications Typical Memory Chip and Package Structure Memory Assembly Process Flow Key Memory Assembly Process Technology and Solution JCET Memory Assembly Status

11:50 am - 12:10 pm

Memory packaging technology - ON-SITE

Wade Liu

Technical marketing Director - Huatian Technology

To be announced soon

12:10 pm - 1:10 pm

Lunch and Networking

1:10 pm - 2:25 am

Session 3 - (1/2) - High-End Packaging and 3D

1:10 pm - 1:35 pm

Keynote: The future of wafer-level 3D IC technologies: Multiple wafer stacking (M-stacking) and Heterogeneous Integration (Hi-stacking) - ON-SITE

Dr. Holly Sun

COO & Senior VP - XMC

With the rapid development of 5G, AI and data center, high bandwidth, high volume and low power consumption are increasingly becoming the key factors restricting chip performance. Wafer-level 3D IC technology as a solution in the post-Moore era has matured so far, such as wafer bonding, through-silicon via (TSV), and hybrid bonding processes. The traditional two-wafer bonding technology has obvious weakness in certain areas, such as the yield, expendability of bandwidth and memory density. In response to these problems, the development of a new generation of wafer-level 3D IC technology has become an urgent requirement. Multi-wafer stacking technology which based on the existing hybrid bonding and TSV platform can realize three-dimensional multi-wafer stacking, and largely increase the bandwidth and density by more than 5 times to meet the needs of data center and HPC. 3D IC Heterogeneous Integration connects chips and wafers with different materials and sizes through advanced bumpless process, which can greatly improve the chip yield and perfectly fit 5G applications.

1:35 pm - 1:50 pm

Collective D2W Hybrid Bonding for 3D SIC and Heterogeneous Integration - ONLINE

Dr. Thomas Uhrmann

Director of business development - EV Group (EVG)

Heterogeneous integration describes the coalescence of multiple developments of the past years. On the one hand, 3D integration technologies have been emerged and are widely available in high volume manufacturing environment. On the other hand, several advanced packaging technologies, such as fan out wafer level packaging or interposers are high volume technologies. Depending on the device architecture and level of integration, several integration methods at different manufacturing levels can be used to create heterogeneous integrated systems. Here we will focus mainly on the 3D stacked IC (3D SIC), bridging the gap between pure backend integration flows such as Fan Out Wafer Level Packaging, and between wafer to wafer integration schemes as done in system on chip integration.Wafer bonding and especially fusion and hybrid wafer bonding are readily available in mass production at major foundries, integrated device manufacturers. While the driving forces for the technology are 3D integration processes for memory, image sensors, this will not be feasible for heterogeneous integration. The major benefit for heterogeneous integration is coming at the system level. However, this means that different silicon nodes, compound semiconductors for photonic, power devices or RF filters coming from different fabs on difference wafer sizes need to find their way on a silicon base substrate. As fusion and hybrid bonding are compatible with front end manufacturing, all sequential die to wafer (D2W) approaches are not. Mainly particle generation and in many cases several hours of placement time, make particle sensitive processes such as fusion bonding very difficult to be integrated for D2W processing. While particle requirements of ISO1 can be mastered inside the equipment, still the population time and moving bond heads over the wafer will influence yields considerably. However, D2W equipment will be detrimental for heterogeneous integration. Combining segmented SYNAPS 2020 – Technical Committee Abstract Review 2 / 2 dies in an advanced package can be done by two different bonding technologies, namely sequential die bonding or a collective die bonding approach. For the collective bonding, individual dies are populated and tacked either on an interposer or a so-called handling carrier, depending on the bonding technology applied. In case of tacking die face-down on an interposer or other active silicon die, bonding is usually being done by thermal bonding. Here, heating and cooling of the substrates are only done once, considerably reducing process cost and thermal budget of the underlying substrate. The second case is tacking the dies face up on a carrier substrate. This reconstructed dies on a carrier can now be processes again on wafer scale, this means preprocessing steps such as direct bonding can be done before bonding the wafers using fusion or hybrid bonding.In this presentation we will show different integration approaches for collective die bonding for fusion as well as hybrid bonding. For both processes, results in terms of die placement and sequential alignment accuracy of the integrated process will be compared and discussed, together with current and potential applications of these processes for future devices.

1:50 pm - 2:05 pm

Advancement in Bonding and Molding Technology for High End Devices - ONLINE

Ruurd Boomsma

Chief Technology Officer - Besi

Advanced packaging is becoming a key technology in advancing the semiconductor industry. The drive towards faster response semiconductor devices requiring lower power consumption and yielding higher overall performance coupled with smaller features is continuing and even accelerating. New applications like 5G, AI, Cloud Computing, Autonomous Driving all rely on new packaging concepts and are at the same time only possible with new packaging concepts. Many new applications may emerge due to improved semiconductor technology. Such packaging technologies may include 2.5D, 3D, SIP and Chiplets and Integrated Photonics based approaches and are becoming now as important as further device shrinking and will become a key enabler for improved overall device performance, new design ideas and new supply chain models In these new packaging technologies, there is a clear trend towards larger die dimensions, more dense contact schemes as well as more variation in device types and structures and thinner dies. This has major impact on the required equipment capabilities in the fields of accuracy, die size and die thickness handling, cleanliness, productivity and flexibility. This presentation will highlight some of the latest technical developments and limitations in Epoxy bonding, Multi Die Bonding and TCB bonding for small pitches and larger die sizes. For even smaller contact pitches Direct Cu-to-Cu bonding will be presented on Die level. New levels of accuracy, placement speeds and cleanliness are key factors for such a process. With these new requirements, back-end equipment is moving to front-end specs. Molding of complex structures and formats including new antenna configurations will also be discussed. SYNAPS 2020 – Technical Committee Abstract Review 2 / 2 Speaker Biography Ruurd Boomsma received a Master Degree in Technical Physics from the State University of Groningen, the Netherlands, in Semiconductor Physics and High Vacuum Technology. He started working in the Semiconductor Industry in 1984 at ASM in Bilthoven, the Netherlands, in front end equipment including Epi, Diffusion, PECVD Implant and Litho and was also involved in the sales of the first steppers from ASML (at that time part of ASM). After that, he moved on to MRC, a USA based company for PVD and Etch equipment. Later he became responsible for the Unaxis (Oerlikon) Materials and Display Divisions. He is now over 10 years active at Besi. Initially involved in technology assessment, supply chain optimization followed by holding the responsibility for the Plating Product group and later fully responsibility for the Die Attach product group. He is now Besi’s Chief Technology Officer and also responsible for strategic supply chain management and overall quality. ABOUT BESI: BE Semiconductor Industries N.V. (“Besi”) is a leading supplier of semiconductor assembly equipment for the global semiconductor and electronics industries focusing primarily on the advanced packaging segment of the market. Besi develops leading edge assembly processes and equipment for leadframe, substrate and wafer level packaging applications in a wide range of end-user markets including electronics, mobile internet, cloud infrastructure, computing, automotive, industrial, LED and solar energy. Customers are primarily leading semiconductor manufacturers, assembly subcontractors and electronics and industrial companies. Besi’s ordinary shares are listed on Euronext Amsterdam (symbol: BESI). Its Level 1 ADRs are listed on the OTC markets (symbol: BESIY Nasdaq International Designation) and its headquarters are located in Duiven, the Netherlands. Research and Development is organized in Switzerland, Austria and the Netherlands. Support and production is in Singapore, Malaysia and China. For more information, please visit our website at www.besi.com.

2:05 pm - 2:25 pm

Heterogeneous Integration - ON-SITE

Wang Qiong An

Senior manager of product marketing department - EA/APMR Business Unit - K&S

The growth of advance packaging especially with Heterogeneous integration and 3D stacking, starting with EMIB (Embedded Multi-die Interconnect Bridge), inFO and CoWoS (Chip-on-Wafer-on-Substrate) and more recently to Foveros, SoIC (System-on-Integrated Chips) and MUST (3D MUlti-STack) technologies, are emerging as a more cost-efficient way to achieve greater integration and IO densities. With this trend of heterogeneous integration, we can overcome Moore’s law and the reliance of few key logic companies with fab capabilities below 10nm. This presentation will discuss the impact of these technologies and requirements they place on Flip chip(FC), backend lithography and Thermo compression bonding (TCB) equipment and how challenes are being addressed.

2:25 pm - 2:55 pm

Coffee break - Networking time

2:55 pm - 3:50 pm

Session 3 - (2/2) - High-End Packaging and 3D

2:55 pm - 3:15 pm

Keynote: Solving test and measurement challenges for 2.5D/3D heterogenous integration challenges - ONLINE

Co-presentation

Amy Leong - CMO, SVP M&A - FormFactor Inc. & Kenan Görgülü - Chief Sales Officer - FRT GmbH Germany a FormFactor company

As wafer level packaging (WLP) and heterogeneous integration (HI) approaches become more relevant, metrology processes are increasingly more complex and diversified. Many new types of measurements are being added to advance yield knowledge of the new chiplet integration processes. FormFactor uniquely offers a wide range of optical and electrical metrology solutions to help reduce the manufacturing cost of these advanced packages. In this paper, we will provide some case studies how FormFactor and FRT (a FormFactor company) flexible products and capabilities help to solve metrology challenges for Advanced Packaging.For electrical test, FormFactor’s MEMS probe cards can test every chips inside a HI packages, supporting test pad/bump pitch as low as 40ums and probe count as high as over 150,000 per probe card. Examples include the SmartMatrixTM 300XP for High Bandwidth Memory (HBM), ApolloTM for Processors and AltiusTM for the fine-pitch interposer.For optical measurement, FRT offers metrology solutions throughout the entire process chain in semiconductors. For FRT’s MicroProf® AP, a comprehensive fully automated tool for advanced packaging applications, features a modular multi-sensor concept, enabling for a wide range of measurement tasks within one metrology tool. It is ideally suited to perform measurement tasks of typical steps in 3D IC manufacturing from various process stages: photoresist coating and structuring, critical dimension (CD) and overlay, through-silicon vias (TSVs) or trenches after etching, isolation and barrier layer deposition, TSV filling, chemical mechanical polishing (CMP), fabrication of redistribution layers (RDLs), under bump metallization (UBM), BGAs, micro and solder bumps, temporary carrier bonding and debonding, backside thinning, reveal of TSV copper nails, dicing and stacking and measurement of mold- and contact pad surfaces. The tool features wafer handling system within an equipment front end module (EFEM) which is able to handle SEMI standard wafers, highly warped wafers (e.g. eLWB), bonded wafers, wafers on tape, TAIKO wafers, bare and thinned wafers, Fan-Out wafers and even panels. With a recipe-driven, full measurement and analysis software, the tool can be easily integrated into the shop floor automation process.

3:15 pm - 3:35 pm

Heterogeneous Integrations: Challenges and Solutions - ON-SITE

Percy Lam

Sales Manager - ASM Pacific Technology

Heterogeneous Integrations (HI) has been known as one of the enablers for More-than Moore (MtM) technologies, mainly contributed by declining profit margins and enormous investment in Tech Node scaling which simply relies on Front-end technologies. The term “Chiplet” thus has become a hot new buzzword in the industry, which can best depict the concept of Heterogeneous Integrations via the means of Advanced Interconnect technologies in packaging and exhibits increasing momentum of the associated technologies in recent years. There exists many well-known process approaches for realizing Heterogeneous Integrations, which can be basically classified as package level and chip level HI. In package level HI, there are 2.5D methods such as CoWoS, EMIB and HIFO (Fan-out based 2.5D package integration). On another level, chip level HI such as FOVEROS and SoIC have even further extended the “Chiplet” concept by making use of Advanced Interconnect technologies such as TCB, hybrid bonding, etc., to maximize the benefits brought by Heterogeneous Integrations. In this presentation, various process challenges specifically on interconnect, and the corresponding solutions including manufacturing equipment solution will be discussed for different Heterogeneous Integrations approaches.

3:35 pm - 3:50 pm

Inspection and Metrology Challenges for Advanced Packaging - ONLINE

Ramy Langer

Chief Operating Officer - Camtek

Semiconductor packaging manufacturing landscape is dynamic and requires all manufacturer types an extent of flexibility to adapt to the constant challenging requirements. These include: • Reducing chip scale • Increasing data rate • Uncompromised reliability at high production rate Specializing in inspection and metrology, Camtek is involved in these challenges and constantly develops dedicated solutions to keep in line with the industry roadmap. Bumps are getting smaller with finer pitch and RDLs are getting ever thinner, while market demands for faster and more accurate metrology tools. Uncompromised high yield requires perfect detection capabilities at smaller and smaller pixel sizes, and defects which are hidden within the substance, such as inner cracks. In a data driven world demanding automatic data sorting of massive quantities, defects classification must be put through a learning system deriving intelligent decisions. Our deep learning system facilitates customer defined classification into an automatic and a more accurate process. Camtek, as an experienced inspection and metrology equipment manufacturer, continuously and successfully adjusts to these challenges. In this presentation I will present some of our inspection and metrology solutions.

3:50 pm - 4:45 pm

Session 4 - Glass Packaging

3:50 pm - 4:10 pm

Keynote: Glass Carriers for Advanced Packaging Applications - ONLINE

Varun Singh

Product Line Manager, Carrier Solutions - Corning

Glass as a temporary carrier material has proven its value in advanced wafer thinning and high- performance fan-out packaging. As these technologies advance, new challenges emerge that require glass innovation.In this presentation, we will discuss recent innovations at Corning that allow the use of glass carriers for mechanical debonding. Glass carriers are extensively used when the final wafer thickness is less than ~30um and low stress laser debonding is used. For applications where Si device wafer is thinned to 50-100um, glass carriers can provide value in visual inspection and can offer a lower cost solution vs Si carrier. Glass carriers can be a drop-in replacement for existing mechanical debonding process.With a rich product portfolio and short delivery time, Corning is positioned to support customers from product development all the way to mass production.

4:10 pm - 4:30 pm

Development of 3D Wafer Level Packaging and Integration Technologies for 5G Applications - ON-SITE

Dr. Daquan Yu

CEO - Xiamen Sky Semiconductor

Wafer level packaging and integration is very important for 5G device integration. Wafer level Fan-in can be used for filters, IPDs, and RF modules. Wafer Level Fan-out can be used for RF modules and mmWave chips. Recently, glass wafer level packaging using through glass via (TGV) technology and embedded glass fan-out (GFO) technology become more and more mature. They can be used for 3D integration for IPD, mmWave, RF module. The advantages of glass wafer packaging include small form factor, low cost, simple process, and excellent electrical performance. There are still a lot of innovation works for the development of Wafer Level System Integration Technology for various 5G applications.

4:30 pm - 4:45 pm

To be announced - ONLINE

Santosh Kumar

Principal Analyst - Yole Développement

To be announced

4:45 pm - 4:50 pm

Thank You and Adjourn

Speakers

C. Key Chung, PhD
SENIOR DIRECTOR OF ADVANCED PACKAGE R&D - SPIL
Hongwen He
In charge of Collaboration Plans with Colleges and Industry - HiSilicon
Sylvester Demmel
Senior Product Manager for SIPLACE Advanced Packaging - ASM Assembly Systems
Ewald Strolz
Head of Process Development - Evatec
David Butler
Executive Vice President and General Manager - SPTS Technologies, a KLA company
Qidong Wang
Director of R&D Department - NCAP
Shen Guoqiang
JSCC WB group R&D Center and Engineering Team Manager - JCET
Wade Liu
Technical Marketing Director of Huatian Technology
Dr. Holly Sun
COO & Senior VP - XMC
Dr. Thomas Uhrmann
Director of Business Development - EV Group
Ruurd Boomsma
Chief Technology Officer - Besi
Wang Qiong An
Senior Manager of Product Marketing Department - K&S
Kenan Görgülü
Chief Sales Officer - FRT GMBH GERMANY A FORMFACTOR COMPANY
Amy Leong
CMO, SCP M&A - FormFactor Inc
Percy Lam
Sales Manager - ASM Pacific Technology
Ramy Langer
Chief Operating Officer - Camtek
Varun Singh
Product Line Manager, Carrier Solutions - Corning
Dr. Daquan Yu
CEO - Xiamen Sky Semiconductor
Santosh Kumar
Principal Analyst - Yole Développement

Sponsored by

PLATINIUM SPONSOR

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LUCKY DRAW SPONSOR

BE Semiconductor Industries N.V. (“Besi”) is a leading supplier of semiconductor assembly equipment for the global semiconductor and electronics industries focusing primarily on the advanced packaging segment of the market. Besi develops leading edge assembly processes and equipment for leadframe, substrate and wafer level packaging applications in a wide range of end-user markets including electronics, mobile internet, cloud infrastructure, computing, automotive, industrial, LED and solar energy. Customers are primarily leading semiconductor manufacturers, assembly subcontractors and electronics and industrial companies. Besi’s ordinary shares are listed on Euronext Amsterdam (symbol: BESI). Its Level 1 ADRs are listed on the OTC markets (symbol: BESIY Nasdaq International Designation) and its headquarters are located in Duiven, the Netherlands. Research and Development is organized in Switzerland, Austria and the Netherlands. Support and production is in Singapore, Malaysia and China. For more information, please visit our website at www.besi.com.

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In the future, NAURA will shine in the world arena as a leading firm in high-end electronic technology equipment and precision electronics, strive for further development and lead the way for the future. Furthermore, NAURA will also stick to customer demand-oriented sustainable innovation to promote the progress of industrial technology and bring infinite possibilities for the industry.

LOGO SPONSOR

In 1957, Japan was finishing postwar reconstruction and starting a period of high economic growth. Petrochemical products were essential for industrial development. JSR Corporation (formerly Japan Synthetic Rubber Co., Ltd.) was established as a national policy concern to pioneer synthetic rubber production in Japan. We later applied our polymer technologies in the fine chemicals sector to produce semiconductor materials, display materials, and other products. JSR is currently taking up the challenge of materials innovation applicable in new fields, including the life sciences, environment and energy that make use of the acquired technologies in the fine chemicals sector. These are under development as future JSR core businesses.

http://www.jsr-sh.com.cn/

LOGO SPONSOR

The SMT Solutions segment within the ASM Pacific Technology Group
The mission of the SMT Solutions segment within the AMS Pacific Technology Group (ASMPT) is to implement and support the smart SMT factory at electronics manufacturers worldwide.

ASM solutions such as SIPLACE placement systems and DEK printing systems support the networking, automation and optimization of central workflows with hardware, software and services that enable electronics manufacturers to transition to the smart SMT factory in stages and enjoy dramatic improvements in productivity, flexibility and quality.

Since maintaining close relationships with customers and partners is a central component of ASM’s strategy, the company has established the SMT Smart Network as a global forum for the active exchange of information between and with smart champions. In addition to being a founding member of the ADAMOS joint venture for the development of an IIoT platform for manufacturing companies, ASM is establishing together with other SMT manufacturers the open HERMES standard as a successor to the SMEMA standard for M2M communication in SMT lines.

For more information about ASM, visit www.asm-smt.com.

GIVEAWAYS & BROCHURES SPONSORSHIP

LexisNexis IP is a LexisNexis company. We are the provider of best-in-class information-based solutions and services to meet the needs of the intellectual property market, government agencies, and the life sciences industry. We have worked in the patent arena with the U.S. Patent and Trademark Office (USPTO) for nearly half a century and offer a suite of IP solutions that deliver the results you need across the patent workflow under the LexisNexis IP name. The corporate culture is driven by a commitment to excellence, innovation, and a strong dedication to our customers, employees and communities. Learn more about LexisNexis Legal & Professional.

EXHIBITOR

Baihe Instruments was founded in Shanghai. Sales Network in China, with east China as the center, for all parts of the country. Is a set of pre-sales support and after-sales service as one of the technical enterprises. The company professional agent sales of advanced materials testing equipment, products from Europe, the United States, Japan and other well-known equipment suppliers in the industry. The company has experienced technical personnel and professional service team in the industry, can provide effective equipment technical support, and even the overall laboratory solutions. The company has a good product supply chain and a complete customer network to better serve the Chinese market.

www.bahens.cn

EXHIBITOR

CoreTech System Co., Ltd. (Moldex3D) was founded in 1995, it has provided the professional plastic injection molding simulation solution “Moldex” series for the plastic injection molding industry, and the current product “Moldex3D” is marketed worldwide.

Moldex3D IC Packaging provides a complete series of molding solutions, and supports comprehensive solutions such as : Transfer Molding, Molded Underfill, Capillary Underfill (CUF), Compression Molding, Embedded Wafer Level Package (EMWLP), and No Flow Underfill (NFU) / Non Conductive Paste (NCP). Auto meshing function supports for user to complete encapsulation analysis more easily. User also can adopt advanced manual meshing for more complex component like undercut-shaped lead frame.

Moldex3D IC Packaging helps designers to fully analyze the chip encapsulation process from filling, curing, cooling, to advanced manufacturing demands, such as filler concentration, underfill encapsulation, post-molding curing, stress distribution, or structural evaluation. Significant molding problems can be predicted and solved upfront, which helps engineers enhance chip quality and prevent potential defects more efficiently. The accurate simulation also helps design optimization and well cost management.

www.moldex3d.com

EXHIBITOR

ERS has been supplying innovative thermal test solutions to the semiconductor industry since 1970 and is famous for fast-ramping and precise low-noise thermal systems (-65°C to +400°C) for analytical, parametric and wafer sort probing up to 300mm. The patented ERS flagship product for hot/cold wafer test, AC3(R), is available for package-level tri-temp applications for MEMS test. We design and build stand-alone thermal-forcing systems and custom production tools for difficult thermal applications. We also supply the advanced wafer level packaging market with its fully automatic debonders and manual warpage adjust tools used in the production of both 200mm and 300mm eWLB device packages. On a broader scale, ERS supports not only eWLB but many other Fan-Out Wafer-Level-Packaging (FOWLP) and Panel-Level-Packaging (FOPLP) technologies. Our headquarter, sales department, engineering center and production facilities are in the Munich suburb of Germering, and we also have sales and support offices in the US, China, Singapore and Taiwan.

Learn more at: www.ers-gmbh.com

MEDIA SPONSOR

Silicon Semiconductor China is the ‘sister’ title to Silicon Semiconductor –the world most respected and authoritative publication, published by ACT International in Hong Kong, reports the latest news, in-depth analysis, and authoritative commentary on the semiconductor industry. It provides for Chinese semiconductor professionals with the business and technology &product information. Its editorial covers semiconductor manufacturing advanced packaging, wafer fabrication, integrated circuits, MEMs, FPDs, etc. The publication serves Chinese semiconductor industry, from IC design, manufacture, package to application, etc.

http://www.siscmag.com/

MEDIA SPONSOR

GSI Media was established in 2015, with the mission of building and serving the semiconductor community with most valuable industry based contents and services. GSI Media is currently one of China’s top-rated media and community brands, thanks to the high quality of contents and its long term commitment to grow the broad base of community. The business of GSI Media ranges from news reporting, market research, headhunting and finance.

Currently there are 5 Wechat public accounts under the GSI Media umbrella,GSI Media has a total of 300,000 readers from semiconductor industry, owns and manages 100+ Wechat communication group. Until today, GSI Media has influenced millions of professionals from semiconductor industry.

Partners

Yole Développement provides market research, technology analysis, strategy consulting, targeted media, and financial advisory services.

With a strong focus on emerging applications using silicon and/or micro manufacturing since 1998, Yole Développement has expanded to include more than 80 collaborators worldwide covering Photonics – Lighting – Imaging – Sensing & Actuating – Display – RF Devices & Technologies – Compound Semiconductors & Emerging Materials – Power Electronics – Batteries & Energy Management – Semiconductor Packaging and Substrates – Semiconductor Manufacturing – Memory – Computing and Software.

The market research, technology and strategy consulting company Yole Développement, along with its partners System Plus Consulting, Blumorpho and PISEO – all part of the Yole Group of Companies-, support industrial companies, investors and R&D organizations worldwide to follow technology trends to grow their business and help them understand the 6 specific markets.

More information: www.yole.fr

HOSTED BY

As an innovation model, National Center for Advanced Packaging Co., Ltd. (NCAP China) was registered in Wuxi New District, China, in September 2012. Supported by Wuxi and Jiangsu government, National Science and Technology Major Project(02 Project) and IC Packaging and Testing Industry Chain Technology Innovation Strategic Alliance, NCAP China, a joint venture with a capital of 234.45 million, is established by ten investors, including the leaders of the IC packaging and testing industry in China (Jiangsu Changjiang Electronics Technology, TongFu Microelectronics, Huatian Technology, Shennan Circuit Company, China Wafer Level CSP, AKM Electronic Technology (Suzhou), Jiangsu CAS Internet-of-things Technology Venture Capital, Shenzhen Fastprint Circuit Tech) and CDB Capital. NCAP’s goal is to establish a national R&D center for advanced packaging and system integration, play a global leading role in the development and commercialization of advanced technologies for microelectronics packaging and system integration, and promote and sustain the technological and commercial advancement of the microelectronics industry in China.

More information: www.ncap-cn.com

#Memory #Packaging #Semiconductor Manufacturing

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