In the quest for cost reduction, the semiconductor industry has always been involved in the development of innovative solutions. End customers are always pushing for low cost packaging solutions, along with higher performance. Panel-level packaging (PLP) shifts packaging from wafer format to strips, and then to large panels.
It generates interest in the market because of its potential cost benefit and higher manufacturing efficiency. It also brings economies of scale due to the large size of the panel and higher carrier usage ratio of 95%, which is much higher than wafer size FO WLP, and enables higher-volume production of large packages. On the application and market sides, many packaging technologies can be considered as PLP, but it is FOPLP (Fan Out Panel Level Packaging) which is attracting most attention, because of the success and awareness of FOWLP (Fan Out Wafer Level Packaging). This attracts players with many different business models, including outsourced semiconductor assembly and test (OSAT), integrated device manufacturers (IDMs), foundries, substrate manufacturers and FPD players. They sense an opportunity to enter the advanced packaging business via fan-out technology.
After years of development, FOPLP is now reality with multiple players starting production between 2018 and 2020. FOPLP is one the fastest growing packaging platforms: the market will show impressive growth between 2017 and 2023 with 79% CAGR, to reach almost US$279 million at the end of the period, reported Yole Développement (Yole) in its Status of Panel Level Packaging 2018 report.
(Source: Status of Panel Level Packaging 2018 – Yole Développement)
Of the many players entering the FOPLP business, Samsung Electro Mechanics (SEMCO) is probably the most aggressive: this leading company invested more than US$400 million in the last 2 years and has finally started production of integrated application processor unit (APU) for its new consumer product, the Galaxy Watch. With this high density FOPLP debut, SEMCO announced its arrival. Using this technology, the Galaxy Watch from Samsung is a huge combination of a PMIC with an application processor environment and a DRAM in the same package, called SiP-ePoP. PMIC and application processor die are placed side by side with an embedded PCB substrate that realizes the top/bottom connection in the packaging.
System Plus Consulting, partner of Yole, offers today a dedicated report, titled, Samsung Exynos 9110 with ePLP: First Generation of Samsung’s Fan-Out Panel Level Packaging.
With the implementation of FOPLP within a smartwatch, Samsung is clearly playing a strategic game within the consumer domain. Beyond the smartwatch, the mobile market could soon be impacted by a possible FOPLP adoption. With this strategic technical choice, SEMCO is clearly targeting TSMC leadership in high-density fan-out packaging, with an aggressive roadmap for FOPLP technology development. The ground is now ready for the battle of giants with, in the foreground, a technology face-to-face in high end fan-out packaging.
Santosh Kumar, Director & Principal analyst, Yole Korea recently interviewed Richard (KwangWook) Bae, Vice President, Head of Corporate Strategy & Planning Team, Samsung Electromechanics (SEMCO) to learn about the recent developments of FOPLP at SEMCO and to understand their vision and perspectives on future of FOPLP business.
Santosh Kumar (SK): Could you please briefly introduce SEMCO and its activities?
Richard (KwangWook) Bae (RB): SEMCO was established in 1973 as an affiliate of the Samsung Group. The full name of SEMCO is Samsung Electro-Mechanics and SEMCO leads the electronic component industry.
Our HQ is located in Suwon, Korea. Overseas plants are located in China, Thailand, Philippines and Vietnam. We also have sales offices in America, Europe, Japan, China, and Southeast Asia.
SEMCO consists of three business units:
• ‘Component Solutions’ which produces passive components such as MLCCs (multilayer ceramic capacitors) and inductors
• ‘Substrate Solutions’ which produces HDI, package substrates and RFPCB
• ‘Module Solutions’ which produces Camera Modules, WiFi Modules.
In 2016, we launched a new division, the FOPLP Division and set up the production line. We started manufacturing FOPLP products for AP(Application Processor)for the Galaxy Watch released in Aug 2018.
SK: Congratulations for being the first player to enter volume production on fan-out panel level packaging (FOPLP).
Can you please explain the SEMCO FOPLP technology, including the panel size and technical specs?
RB: We are manufacturing FOPLP using 510x415mm size Panel, but we’ve already developed panels up to 800x600mm. So, the panel size could be changed according to customer requirements.
Our FOPLP for the Galaxy Watch has 3 RDLs (Re-Distribution Layers) + 1 BRDL (Backside RDL). We applied a PoP structure to Multi Die for AP and PMIC. By applying FOPLP, we could reduce the PKG thickness by more than 20%, which improved the electrical and thermal performance and contributed to expanding the battery capacity.
(Courtesy of: Semco)
SK: By entering fan-out packaging business, SEMCO has entered the field dominated by OSATs & one big foundry player. How do you see the challenge? Whom do you consider your bigger competitor in fan-out packaging business: foundries or OSATs. In the future, do you have plan to expand your packaging services portfolio?
RB: The semiconductor industry will be divided into two areas.
• Where the unique business still exists: Foundry, OSAT, Substrate company maintaining their own business;
• Where the supply chain is ambiguous and the boundary between front-end and back-end is collapsing.
Basically, we think that the Foundries, OSATs and Substrate companies’ own businesses will be maintained in the future. However, in the area where front-end and back-end integration occurs, I think three conditions are required:
- Large scale investments
- Overcoming technology hurdles
- Overcoming supply issues on advanced node wafers.
SK: In the industry, there is some skepticism about the panel level fan-out packaging feasibility from the economic point of view. Most players believe the industry is still not ready for panel level fan-out as the market is not large enough to keep the line busy. What is your opinion on this?
RB: In the first place, the single die PKG such as AP, PMIC, etc. requires mass production, so the demand is expected to be sufficient. We are working with customers to respond to their requirements. In addition, for heterogeneous integration and FOSiP, several dies are packaged into a one large PKG. Panel level is more competitive than wafer. As the package sizes are increasing, the wafer area usage is decreasing. So, in the case of FOSiP, the number of PKG from a panel is more than from the wafer. For these reasons, FOPLP should be advantageous for heterogeneous integration or FOSiP. Market demand for various applications will also continue to increase.
SK: What is the sweet spot for fan-out on panel packaging in terms of die/package size? How much cost reduction do you expect by moving to panel format for such package sizes?
RB: Currently FOPLP is mainly used for mobile applications. But in the near future, FOPLP will expand to heterogeneous integration where size is more than 15×15.
By 2020 or 2021, due to 5G, AI, autonomous driving and server requirements, demand for modularity and high-speed data processing will increase dramatically. FOPLP can meet these demands, so in multi die PKG, FOPLP will be the mainstream.
The comparison between FOPLP and FOWLP has been discussed only in terms of cost. However, I think there are two types of application for FOPLP, one cost-driven while the other is performance-driven. In the cost-driven sector, FOPLP is advantageous in terms of productivity. However, in terms of performance-driven applications, FOPLP is superior on finer pitches due to the architectural structure of SEMCO’s own design which also improves thermal and electrical performance. So, it is suitable for both the Fan-out SiP and Heterogeneous Integration.
(Source: Samsung Exynos 9110 with ePLP: First Generation of Samsung’s Fan-Out Panel Level Packaging – System Plus Consutling)
SK: SEMCO is one of the key substrate suppliers. How do you see the wide adoption of fan-out packaging adversely affecting the substrate business? What is the strategy of SEMCO to deal with this situation?
RB: SEMCO has been preparing for embedding technology for passive and active devices for more than 10 years. Since the semiconductor node is shrinking, we think that the package substrate should be changed.
Based on these preparations, we developed FOPLP on time and actively responded to the market which needed fan-out PKG such as premium AP, memory and small IC.
We specialize in electronic components, such as passive components including MLCC, substrates and modules, for example. So we can optimize FOSiP by customizing other components.
In addition, there are applications which continuously need current PKG substrates. Not all applications are converted from substrate to PLP. So, it is not a zero-sum game. Moreover, the substrate business will support the FOPLP business.
Based on both substrate and PLP technology, we will respond to customer needs and technology changes.
SK: What applications and device segments are you targeting for FOPLP?
RB: SEMCO started world’s first mass production of FOPLP for Galaxy Watch AP. Also, we expect to apply our FOPLP to not only small ICs but HPC such as AI, 5G, automotive and server. In particular, we developed next generation modules (FOSiP; Fan Out SiP) for various applications.
SK: Many equipment suppliers have developed tools for panel scale fan-out technology. From your perspective, what gaps in the equipment supply chain is remaining that needs to be addressed?
RB: SEMCO has been co-developing FOPLP with global equipment companies since 2015. We have received sufficient support from those companies, so there are no problems in the future.
SK: Standardization of panel size is one of the bottle necks for panel level fan-out adoption. Multiple players are working on different panel sizes. How do you think this issue will be resolved?
RB: We are using a 415×510 panel size because it is the most efficient size for our current applications. Also, in the market, our panel size is considered to be sufficient for current applications.
As SEMCO has a substrate business, we already have mass production experience in larger panel sizes. We utilize these assets for the FOPLP business. We can respond flexibly to changes in panel size and there won’t be any handling problems if we do.
For cost driven applications, there are several suppliers who are currently developing FOPLP. In this case, if panel size, carrier and materials are standardized, I think it will be helpful for the FOPLP ecosystem.
SK: Do you see special requirements for materials such as molding compound, dielectric materials, plating chemistry for FOPLP as compared to FOWLP?
RB: Basically, FOWLP and FOPLP use similar PID materials, equipment and conditions. The differences are the type of carrier which varies in shape and materials.
SK: What are the key technical challenges for FOPLP? How do you address these challenges?
RB: Technical issues in FOPLP are RDL formation over large area, DoF margin, die shift, warpage handling and particle control. SEMCO has already resolved these challenges and they are under control.
SK: How do you see the evolution of FOPLP market? What are the key roadblocks you see for its wider adoption?
RB: By 2020 or 2021, due to 5G, AI, autonomous driving and server, semiconductors will become more sophisticated. Simultaneously, this will require high-speed data transfer between memory and logic die. Since FOPLP enables high-speed data transfer by multi-die packaging, it promotes wider adoption of FOPLP.
SK: Do you think that the panel level fan-out roadmap will align with (or even outpace) the wafer level fan-out one, in terms of package capability such as going to 2/2 L/S (and even lower) and heterogeneous integration (SiPs) ? Where can we see the SEMCO FOPLP roadmap heading in next 5 years (in terms of package design parameters such as RDL L/S and number of layers, pitch, thickness, size etc.)?
RB: As mentioned earlier, FOWLP and FOPLP are similar technologies. So basically the roadmap and target applications are similar.
However, there is a difference in the pitch specification of PoP Stack. Due to the structural difference, our PLP can attain a finer pitch. In addition, PLP has the advantage of not requiring die bumps.
As a JEDEC standard, 2/2 L/S will be sufficient for high-end applications such as HPC or FOSiP in the future. L/S less than 2/2 will be rarely needed and it is considered as a niche market only for some special products.
Richard (KwangWook) Bae, Vice President, Head of Corporate Strategy & Planning Team, Samsung Electromechanics (SEMCO)
Santosh Kumar is currently working as Director Packaging, Assembly & Substrates, Yole Korea. He is involved in the market, technology and strategic analysis of the microelectronic assembly and packaging technologies. His main interest areas are advanced IC packaging technology including equipment & materials. He is the author of several reports on fan-out / fan-in WLP, flip chip, and 3D/2.5D packaging.
He received the bachelor and master degree in engineering from the Indian Institute of Technology (IIT), Roorkee and University of Seoul respectively. He has published more than 40 papers in peer reviewed journals and has obtained 2 patents. He has presented and given talks at numerous conferences and technical symposiums related to advanced microelectronics packaging.
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