FOWLP is the fastest-growing packaging platform, adopted for various applications from mobile and automotive to medical and packaging, for both low-end (i.e. audio codecs) and high-end devices (i.e. APU). However, cost is still a concern compared to other mature packaging platforms, and end-customers are always pushing for a lower price.
One way to reduce cost is to process the fan-out package from wafer to large-panel level. This brings economies of scale and a higher carrier usage ratio, resulting in higher manufacturing efficiency and an overall lower cost per package. Thus, fan-out panel-level packaging (FOPLP) is currently attracting huge interest in the industry from players with diverse business models. These include outsourced semiconductor assembly & test (OSAT), integrated device manufacturers (IDMs), foundries, substrate manufacturers, and FPD players, all of whom sense an opportunity to enter the advanced packaging business via fan-out technology.
After years of development/qualification/sampling, FOPLP is finally moving into volume production – and nepes is one of the key market entrants. nepes is continuously developing products for a variety of applications, and its sensor IC product is under LVM. nepes’ HVM on-panel will start in Q4 2018 and ramp-up to full-scale from 2019. Once it’s fully operational, the FOPLP market is expected to reach ~ $280M in 2023 at a CAGR 2018-2023 of 79%.
Jason Park, marketing director at nepes shares the corporation’s vision on FOPLP with Santosh Kumar, Director, Packaging, Assembly & Substrates, Yole Korea and author of the report: Status of Panel Level Packaging 2018.
Courtesy of nepes
Santosh Kumar: Can you briefly introduce nepes and its activities?
Jason Park: nepes is a leading-edge provider of wafer-level packaging, panel-level packaging, and turnkey assembly solutions including testing and DPS services. Since 2001, nepes has provided OSAT services in partnership with fabless and IDM customers worldwide. nepes provides an extensive range of packages: bump, WLP, FO-WLP, and FOWL-SiP, as well as 2D and 3D modules. nepes’ PLP has revolutionized the mass-production of advanced semiconductor packages, providing price competitiveness by utilizing an innovative process and structure based on extensive touchscreen panel (TSP) and LCD production experience.
SK: nepes was one of the first players to start FOPLP production. Please explain FOPLP technology?
JP: Panel-level packaging (PLP) is a process in which chips are assembled or packaged at the panel level, either on a rectangular or square format. FOPLP is a migration of fan-out packaging to rectangular format. Using an innovative process and structure, FOPLP provides a solution that increases productivity while reducing manufacturing costs.
SK: What is the status and timeline of FOPLP production?
JP: FOPLP is continuously developing products with a variety of applications. Also, sensor IC product is under LVM. Looking ahead, HVM will start in Q4 2018 and ram up to full-scale in 2019.
SK: nepes is an established FOWLP player (with RCP technology), which is a fast-growing market. What is the rationale behind additional investment in a FOPLP line?
JP: Advanced packaging solutions are used in various fields such as mobile, TV, and automotive, and they are constantly evolving into thinner, smaller forms while boasting high integration and performance. However, advanced packaging solutions are insufficient for achieving significant cost reduction. Thus, nepes developed FOPLP based on our existing fan-out tech and LCD processing experience. Also, since 2011 nepes has possessed hybrid package manufacturing technology that combines LCD line for TSP (touchscreen panel). Moreover, our FOWLP mass production experience dates back to 2009.
SK: From an economics point of view, there is some industry skepticism regarding panel-level fan-out packaging’s feasibility. Most players believe the industry is still not ready for panel-level fan-out since there is not yet a sufficient market to keep the line busy. What is your opinion on this?
JP: Currently, panel-level fan-out does not have enough market to fully load the FOPLP line. However, the semiconductor business and the current IT market, along with new markets like 5G, autonomous cars, and medical parts will all be at the center of the 4th industrial revolution. Moreover, the synergy of next-generation PKG technologies like Stack PKG and 2.5mD PKG is expected to further increase FOPLP’s application.
Courtesy of nepes
SK: What is the sweet spot for fan-out on-panel packaging in terms of die/package size? How much cost reduction do you expect by moving to a panel format for your desired package size?
JP: Customers expect a cost reduction of about 30% from the existing 6×6 package and higher package sizes. Our goal is to meet these expectations.
SK: What application and device segments are you targeting for FOPLP?
JP: In many market applications, FOPLP is being applied in a variety of sensors. nepes is targeting sensor devices for mobile phones (because of their volume, which enables line optimization) and fingerprint sensors, which reflects a reduction in PLP cost.
SK: On average, what is the cost?
JP: Multi-die PKG is the main product, but it is difficult to set an average price because the cost varies depending on die/component quantity. Our goal is to provide a 20% – 30% lower price compared to existing packaging. Achieving this will allow us to promote PLP growth.
SK: Many equipment suppliers have developed tools for panel-scale fan-out technology. From your perspective, what remaining gaps in the equipment supply chain need addressing?
JP: FOPLP panel size, compared to existing 300mm FOWLP panel size, is being developed with different specifications by OSAT companies. It is known that FOPLP has the largest size (600 x 600mm) out of many standards. Ultimately, it will require the standardization of equipment for sputtering, photo, plating, and etching in order to cover this specification and for automation infrastructure (i.e. handling production lines).
SK: Do you foresee special requirements for materials such as molding compound, dielectric materials, and plating chemistry for FOPLP compared to FOWLP?
JP: With FOPLP, the main process control items are die drift and warpage control. The development of materials that can improve package performance while improving these items will continue to be required. In addition, in terms of evaluating the mass production of materials developed by suppliers, nepes is a FOPLP leader and is able to secure its maturity and marketability through collaboration with suppliers.
(Source : Status of Panel Level Packaging 2018 – April 2018)
SK: What are FOPLP’s key technical challenges, and how do you address them?
JP: As mentioned earlier, for FOPLP’s die-drift and warpage control, nepes has designed effective methods to improve these items and provide an opportunity to start LVM.
SK: How do you see the FOPLP market’s evolution? What are the key roadblocks hindering its wider adoption?
JP: Core fan-out products and high-density fan-out products coexist in the fan-out market. FOPLP is targeted as the low-cost version of existing fan-out and will ultimately increase development completion of high density fan-out products. However, it is likely there will be mass-production of core fan-out products that are easy to implement during a certain period.
SK: Where do you see nepes’ FOPLP roadmap heading over the next five years in terms of package design parameters like RDL and L/S, along with number of layers, pitch, thickness, size, etc.)?
JP: The aforementioned core fan-out product (aka conventional fan-out product) is expected to be covered at L/S 10/10 and 500 I/Os. However, to mass produce high-density fan-out products, it must be possible to implement less than L/S 5/5 and more than 500 I/Os. Also, nepes is currently developing a package thickness that minimizes multi-layers and will assist with increasing TRM market visibility after Q4 2018, when HVM of FOPLP begins in earnest.
Jason Park has been in the semiconductor area for 22 years with specialty of sales and marketing based on previous his experiences with planning, purchasing and program management. He has started his work in Samsung Electronics in 1996 as a purchasing of electrical components for Video, Camcorder and Cameras. After that, he joined fabless Company (Leadis Technology) as global operation and program manager for handling Fabs, OSATs from 2003. In 2009, He joined as marketing director for overseas customers in nepes Corporation. He is currently working with global top tier customers located in US, EU, TW and CN..
Santosh Kumar is currently working as Director, Packaging, Assembly & Substrates at Yole Korea. He is involved in the market, technology and strategic analysis of the microelectronic assembly and packaging technologies. His main interest areas are advanced IC packaging technology including equipment & materials. He is the author of several reports on fan-out / fan-in WLP, flip chip, and 3D/2.5D packaging.
He received the bachelor and master degree in engineering from the Indian Institute of Technology (IIT), Roorkee and University of Seoul respectively. He has published more than 40 papers in peer reviewed journals and has obtained 2 patents. He has presented and given talks at numerous conferences and technical symposiums related to advanced microelectronics packaging.
Status of Panel Level Packaging 2018
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