FOPLP vs. FOWLP: the battle between two giants, Samsung and TSMC

In the quest for cost reduction, the semiconductor industry has always been involved in the development of innovative solutions. One approach currently considered by the leading semiconductor players is the migration from wafer and strip size to large size panels dedicated to IC assembly. Efficiency and economies of scale are clearly the added-value of this path.

Moving fan-out package manufacturing from wafer, FOWLP, to large scale panel, FOPLP, could be the solution for a wider adoption. The FOWLP market is expected to show significant growth of 20% between 2018 and 2023, reaching about US$ 2.3 billion by 2023. FOPLP technology is now a reality after years of development and could become a serious threat, announced Yole Group of Companies, including System Plus Consulting and Yole Développement (Yole). And therefore, according to the Group, many players are moving to high-volume manufacturing in 2018 or 2019. 

One of them, Samsung Electro Mechanics (SEMCO), is probably the most aggressive: this leading company invested more than US$400 million during the last two years and has finally begun production with integrated APE for its new consumer product, the Galaxy Watch. With this strategic technical choice, SEMCO is clearly targeting TSMC’s leadership in high-density fan-out packaging, with an aggressive roadmap for FOPLP technology development. With this high density FOPLP debut, SEMCO has announced its arrival.

According to the Status of Panel Level Packaging 2018 Report from Yole, FOPLP is one of the fastest growing packaging platforms: the market is expected to show impressive growth between 2017 and 2023, with a 79% CAGR to reach almost US$279 million at the end of the period.

The battleground is now ready for the battle of giants, face to face in high end fan-out packaging.


Panel Level Packaging report
(Source: Status of Panel Level Packaging 2018 – April 2018)

With its attractive volumes, the smartphone industry is an unforgiving competitive landscape. Technology choices and manufacturing strategies are key to dominate this industry and ensure leadership.

Samsung is manufacturing its own processors, based on in-house packaging solutions. This strategy allows the company to control the whole supply chain, from die to final product.

Competitors like Apple, however, outsource the processor manufacturing to key partners. Two year ago, Apple decided to use an FOWLP-based technology released by TSMC, namely inFo. This approach clearly announced the birth of a new era in the packaging industry, bringing the Fan-Out approach to the consumer market.

Advanced packaging wafer split by business model – 2017 (Source: Status of the Advanced Packaging Industry 2018 – September 2018)

The smartwatch market is a specific world. Dimensions and integration requirements are extremely aggressive. The objective is to get a slicker watch design with bigger battery space. With the growth of demand for small size and slim z-height packaging, SEMCO adopted a newly developed FOPLP-based solution, in direct competition with the well-known inFo from TSMC. The timing is perfect: for the first time, FOPLP technology penetrates the consumer market.

Using this technology, the Galaxy Watch from Samsung features a combination of a PMIC with an application processor unit and a DRAM in the same package, called SiP -ePoP. PMIC and APE are placed side by side in an embedded structure that realized the top/bottom connection in the packaging. This approach could drastically reduce the packaging cost. Beside the cost advantage, SEMCO managed to get a line/space around 10 µm, a dimension that is comparable to TSMC’s InFo technology.

With the implementation of FOPLP within a smartwatch, Samsung is clearly playing a strategic game within the consumer playground. Beyond the smartwatch, the mobile market could soon feel the impact of FOPLP adoption. This strategic positioning is part of a wider competition in advanced packaging between Samsung and TSMC. These two companies have processed approximatively 1,8 million wafers and 2,3 million wafers respectively in advanced packaging, according to the Status of Advanced Packaging 2018 Report from Yole.

One can ask how much business is left to the OSATs, and what strategy will be adopted by OSATs to respond. The recent announcement by Power Tech International that it is investing US$ 1500 million in Fan-Out panel-level packaging indicates that the competition is not yet over and will be continued in the advanced packaging field in the coming months.

In this competitive ecosystem, System Plus Consulting has expanded its efforts and research capacities to get a better understanding of the technology choices made by the leading smartphones companies. 
The reverse engineering and costing company is working closely with Yole’s analysts, to figure out and analyze the technologies and identify the technical challenges and market opportunities.

A reverse costing report dedicated to the FOPLP Package of the Exynos Processor in the Galaxy Watch is available today. It offers a comprehensive description of the packaging, highlighting innovations and differences: PCB substrate, RDL, manufacturing process flow and more are part of this analysis. In addition, System Plus Consulting analysts propose a detailed comparison: FOPLP vs. FOWLP.


Photo Stephane Elisabeth SYSTEM PLUS CONSULTING YOLE 2018

Dr. Stéphane Elisabeth has joined System Plus Consulting team, as a Project Manager, to provide his deep knowledge in RF application, materials characterizations and Electronics systems. He is in charge of Imaging, RF and Packaging projects.

Stéphane holds an Engineering Degree in Electronics and Numerical Technology, and a PhD in Materials for Microelectronics.

Photo Santosh Kumar YOLE 2018

Santosh Kumar is currently working as Director & Principal Analyst Package, Assembly and Substrate at Yole Korea, part of Yole Développement (Yole). He is involved in the market, technology and strategic analysis of the microelectronic assembly and packaging technologies. His main interest areas are advanced IC packaging technology including equipment & materials. He is the author of several reports on fan-out / fan-in WLP, flip chip, and 3D/2.5D packaging.
He received the bachelor and master degree in engineering from the Indian Institute of Technology (IIT), Roorkee and University of Seoul respectively. He has published more than 40 papers in peer reviewed journals and has obtained 2 patents. He has presented and given talks at numerous conferences and technical symposiums related to advanced microelectronics packaging.

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