As reported in “Fan-Out Packaging: Technologies and Market Trends 2019” and “Status of Panel Level Packaging 2018” from Yole Développement (Yole), key players from all kinds of business models have adopted Fan-Out packaging. The core FO (Fan-Out) market confirmed its stability, with significant new entrants joining via FOPLP. Although existing FOWLP players have a long history of established qualifications, mid-end devices may be too costly for FOWLP players.
PTI has invested in, developed, and started LVM FOPLP production for MediaTek. FOPLP will emerge as a cost-effective option in core market. In HD FO, TSMC has extended its leadership even further by rolling out inFO-oS for HPC application. Exciting developments for new applications are underway with inFO-AiP and inFO-MS. TSMC’s aggressive roadmap to develop sub-micron RDL L/S may create a new market segment, UHD FO (Ultra HD FO). SEMCO has achieved a new milestone by enabling FOPLP for APE+PMIC in Samsung Galaxy smartwatch. Although this is still considered Core FO in terms of I/O density, it will not be long before SEMCO goes high-end to challenge TSMC for Apple’s APE business.
FOWLP is the fastest growing packaging platform and has been adopted for various applications from mobile to automotive to medical, for packaging both low-end (e.g. audio codecs) and high-end devices (e.g. APUs). However, cost is still the concern compared to other more mature packaging platforms. End customers are always pushing for lower cost. One of the ways to reduce the cost is to process Fan-Out from wafer-level-packaging to the larger panel-level-packaging. This brings economies of scale and higher carrier usage ratio which results in higher manufacturing efficiency and overall lower cost per package. So, FOPLP is currently attracting huge interest in the industry and is attracting players with many different business models, including OSATs, IDMs, foundries, substrate manufacturers and FPD players. They sense an opportunity to enter the advanced packaging business via Fan-Out technology. After years of development/qualification/sampling, FOPLP is finally moving into volume production with 3 players viz. PTI, NEPES and SEMCO entering this market. The FOPLP market is expected to reach ~ US$280 million in 2023 at a CAGR 2018-2023 of 79%.
(Source:Fan-Out Packaging: Technologies and Market Trends 2019 – Yole Développement)
Different equipment and material suppliers are involved in the FOPLP business. ERS Electronic GmbH is one of the key players that offer tools for thermal debonding and warpage adjustment for both FOWLP and FOPLP. ERS has already established a strong foothold in the FOWLP market with multiple tools installed at various customers. For FOPLP, they offer manual, semiautomatic and, soon to be released, the first fully automatic tools (ADM600SQ) for thermal debonding and warpage adjustment of panels of up to 600x600mm. In terms of equipment readiness for FOPLP, automated debonding is still the bottleneck and with the release of their new tool, ERS aims to solve this issue.
Favier Shoo (FS), Technology & Market analyst, Yole Développementand Santosh Kumar (SK), Director & Principal analyst, Yole Korea had the opportunity to debate with Laurent Giai-Miniet, CEO & CSMO at ERS electronic GmbH (LGM), about the recent developments of FO and FOPLP technologies and understand his vision of the industry evolution:
Yole Développement (YD): Please introduce ERS, its history, product line & current activities?
Laurent Giai-Miniet (LGM): ERS electronic GmbH has 50 years of experience in manufacturing thermal solutions and thermal chucks for the semiconductor wafer probing industry.
We shipped in excess of 5.000 thermal chucks to the semiconductor wafer probing market since the early 70’s and estimate that 80% of those Thermal Chucks are still in use today.
With cultivated expertise in the scope of thermal control we expanded our portfolio since 2008 to offer thermal debonding and warpage adjustment solution for Fan-Out Wafer Level Advanced Packaging market. We have delivered more than xx machines worldwide leaving perhaps the largest footprint in thermal debonding and warpage for FOWLP space making ERS a major player in the fast-growing business of Fan-Out Wafer Level Packaging (FOWLP) machinery market. Our Customers have manufactured more than 2 billions eWLB chips using one of our flagship machines.
After years of development, Fan-out PLP has finally become reality with various players already in production or planning to enter HVM in 2019. What are ERS’ tools/solutions for Fan-out PLP? ERS electronic GmbH offers manual, semiautomatic and soon, the first fully automatic tools (ADM600SQ) for thermal debonding and warpage adjustment of panels of up to 600x600mm. The release of this fully automatic tool for debonding and warpage adjustment is an essential step in the manufacturing of mold compound panel Fan-Out PLP.
YD: Are you also active in the Fan-out WLP market? Do you think that current wafer level tools can be scaled to support panel level packaging? Or do you think PLP tools need to be designed from scratch?
LGM: Most of our business remains in wafer form (FOWLP), Thermal Debonding and Warpage, automatic or semi-automatic machinery. However, ERS electronic GmbH is currently receiving a lot of opportunities for panel debonding for up to 700x700mm. Although, it has proven to be challenging, a lot of tools and technologies will still be applicable moving from 300mm and 330mm wafer format to a square or rectangular panel.
YD: How do you see the evolution of the FOPLP market? What are the key roadblocks to its wider adoption?
LGM: The cost of equipment and the difficulty to upgrade machines from FOWLP to FOPLP will be an obstacle. Also, the lack of “one standard,” for the panel’s dimension hinders fast adoption and endorsement of the technologies by the material manufacturers.
YD: In the industry, there is skepticism about the feasibility of panel level fan-out packaging from an economics point of view. Therefore, most players believe the industry is still not ready for such an approach as the market is not big enough to keep the line busy. As an equipment supplier, how do you respond to this concern?
LGM: There maybe an excess capacity in place shortly for Fan-Out Wafer Level Packaging (FOWLP) but this is punctual I reckon, as demand continues to raise. In the 2019 context, some people may become hesitant to upgrade to Panel manufacturing. In the meantime the old 200mm FOWLP capacity is likely to become obsolete and by essence of the devices manufactured in Fan Out technologies (SoC´s for IoT, for SmartPhone, for driving assistance in Automotive etc) the demand is raising quickly.
The skepticism is coming from the fact that OSAT and others were deploying capacity for FOWLP, while the demand for Panel grew, causing confusion in the industry. However, eWLB and small or mid-sized density FOWLP remain the most popular approach for reconstituted wafers. Some customers are in fact still very happy with their 200mm reconstituted wafers and eWLB is and remain the most cost-effective technology for reconstituted wafers whatever the format.
One of the key challenges for an equipment supplier is the lack of standardization of panel size in the industry. Indeed, each company has its own panel size and process.
YD: How do you deal with such an issue?
LGM: It is certainly a significant challenge. At ERS we ensure to talk to as many members of the semiconductor industry as we can to develop solutions that can scale to 600x600mm or 710x650mm. This strategy prevents us from being anchored to a specific panel size. At ERS we do everything in our hands to remain technologically nimble and able to adapt to our customers’ needs.
YD: According to ERS, what are the applications and promising markets that could change the industry landscape and the positions of the leading equipment manufacturers in the panel packaging area?
LGM: The applications and markets that are most likely to drive change in FOWLP are System-On-Chip (SOC), Mobile, Automotive Radar, and connectivity devices for the Internet of Things (IoT). Another promising application is large System in Package (SiP), due to the yield problems that arise when using a round format. Today, equipment makers are better positioned for FOPLP since panel front end machines already exist.
YD: Some of the tool suppliers for FOPLP leverage their experience from FPD/PCB/Solar industry. Do you also leverage experience from other industries to design and develop tools for FOPLP?
LGM: Currently, ERS leverages its experience at handling Printed Circuit Board (PCB) concepts and Flat Panel Display (FPD) when developing tools for FOPLP.
YD: What are the key technical challenges for Fan-out PLP? How will ERS’s tools address it?
LGM: In my opinion, die shift, panel warpage and carrier handling remain the key technical challenges for FOPLP.
At ERS we are able to predict and reproduce die shift due to our experience working with thermal control and thorough the understanding of its effect to die displacement. This expertise in thermal manipulation has also enabled us to create a high level know-how to resolve different warpage profile of different FO structure. At ERS, we are experts in handling the metal carrier at very hot temperatures. ERS offers its own vacuum chucks to handle this issue efficiently and in a reliable manner. If the handling of the carrier is not done properly, the debonding process is usually broken. ERS’s experience handling with care the metal carrier allows our customers to have more cost-efficient operations and better yield.
YD: Could you please describe the competitive advantages of your FOPLP product lines?
LGM: ERS has been one of the few companies that have a High-Volume Manufacturing experience. We have been doing this since early 2008, and more than two billion chips have already been processed on ERS thermal solutions.
ERS’s experience processing eWLB’s material is definitely an advantage since it is the same material used in the FOPLP. In our eWLB Competency Center in Munich, we have handled 100’s of Panel (Square or rectangular) and other reconstructed wafers types (from very thin to heavy die content and heavy loaded wafers) and we have always allowed our Customer some free trial. We believe we are experts at handling the multiple difficulties that arise while handling this type of advanced material.
Finally, ERS is an engineering company that has worked on thermal management solutions within the semiconductor industry for nearly 50 years. This experience has enabled us to prevent and deal efficiently with warpage which is a temperature dependent issue.
YD: Apart from your current equipment portfolio that addresses specific FOPLP manufacturing challenges, are there any other challenges on which ERS is working for which ERS could introduce solutions or tools in the future?
LGM: We are currently working on very important projects to solve the new challenges that the Semiconductor back-end industry faces e.g. wafer testing of Sensors where high thermal uniformity is required. We are also working on a specific solution for MEMS probing and also a thermal management solution for Ashing process in front-end manufacturing.
YD: Is there anything else you would like to share with I-Micronews’ readers?
LGM: Yes, definitely. ERS is gaining a distinguished industry expert, Debbie-Claire Sanchez. She worked for more than seven years in the field of wafer level packaging, both fan-in and fan-out. She focused the last five years of her career on fan-out wafer and panel level reconstruction process development with DECA Technologies (Philippines). She was recently in charge of an account development and associated technology transfer in Taiwan.
Laurent Giai-Miniet is the CSMO and CEO of ERS electronic GmbH. He is responsible of ERS’s sales, marketing, applications and business development. He has more than 25 years of experience in the semiconductor industry and has held leadership positions in renowned companies such as Texas Instruments and Infineon, as well as in high-tech start-ups. Laurent holds an MBA from the Institut d’Administration des Entreprises of Aix-en-Provence (France).
Favier Shoo is a Technology and Market Analyst in the Semiconductor & Software division at Yole Développement, part of Yole Group of Companies. Favier is engaged in the development of technology & market reports as well as the production of custom consulting.
After spending 7 years at Applied Materials as a Customer-Application-Technologist in advanced packaging marketspace, Favier had developed a deep understanding of the supply chain and core business values. Being knowledgeable in this field, Favier had given trainings and held numerous technical review sessions with industry players. In addition, he had obtained 2 patents.
Prior to that, Favier had worked at REC Solar as a Manufacturing Engineer to maximize production capacity.
Favier holds a Bachelor in Materials Engineering (Hons) and a Minor in Entrepreneurship from Nanyang Technological University (NTU) (Singapore). Favier was also the co-founder of a startup company where he formulated business goals, revenue models and marketing plans.
Santosh Kumar is currently working as Principal Analyst and Director Packaging, Assembly & Substrates, Yole Korea. He is involved in the market, technology and strategic analysis of the microelectronic assembly and packaging technologies. His main interest areas are advanced IC packaging technology including equipment & materials. He is the author of several reports on fan-out / fan-in WLP, flip chip, and 3D/2.5D packaging.
He received the bachelor and master degree in engineering from the Indian Institute of Technology (IIT), Roorkee and University of Seoul respectively. He has published more than 40 papers in peer reviewed journals and has obtained 2 patents. He has presented and given talks at numerous conferences and technical symposiums related to advanced microelectronics packaging.
Samsung and PTI, with panel-level packaging, have entered the Fan-Out battlefield. – Get more here
Panel level packaging players are ready for high volume production. – Get more here
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