Although Moore’s Law has remained alive for over five decades, it is no longer cost-efficient. When it comes to advanced lithographic nodes, lesser manufacturers can keep up.
“Now, there are only three leading-edge players, Intel, Samsung and TSMC”, announces Favier Shoo, Technology & Market Analyst, Advanced Packaging at Yole Développement (Yole). “The industry is today diligently using advanced packaging technologies to put multiple advanced and/or mature chips in a single package, which is also known as heterogeneous integration. Together with 2.5D/3D packaging this extends Moore’s Law at system-level.”
Without a doubt, times have changed, high-end performance packaging is enabling system-level 2.5D/3D integration trend. This is not only sustained but accelerating into new highs because the industry is seeking alternative to design & manufacture latest SoC using SiP and chiplet based approach by leveraging different Advanced Packaging technologies and a mix of both latest & matured nodes, announces the market research & strategy consulting company Yole in its new advanced packaging report, High-End Performance Packaging: 3D/2.5D Integration.
Released this week, this new technology & market report, presents a comprehensive overview of the high-end technologies, classified as high-end performance packaging. According to Yole’s advanced packaging analysts, high-end performance packaging is defined as a forefront packaging technology, which value-adds device performance with high IO density (≥16/mm2) and fine IO Pitch (≤130µm).
In this dynamic context, Yole’s report identifies and analyzes the key market drivers, benefits and challenges of high-end performance packaging technologies by application. With a detailed description of each technologies, their trends and related roadmaps, this study proposes an overview of the supply chain and analyzes the competitive landscape. In addition, this report provides detailed market figures and estimates future trends…
Yole’s partner, System Plus Consulting announces in parallel, a reverse engineering & costing report focused on the hybrid advanced packaging solution proposed by Intel: Intel Foveros 3D Packaging Technology.
“Intel has developed several interconnect technologies to enable heterogenous integration using chiplets”, comments Stéphane Elisabeth, Technology & Cost Analyst from System Plus Consulting. “An early glimpse of the technology enablers was seen in 2018 on an Intel processor, then called EMiB. Today, Intel shows another way to interconnect dies in processor using an active interposer and Foveros technology.” … Full story
Related Reports and Monitors
(x)PU: High-End CPU and GPU for Datacenter Applications 2020
Market & Technology
WLCSP/ Fan-In Packaging Technologies and Market 2020
Market & Technology