With higher performance, lower consumption and smaller footprint, stacking technology is becoming standard for high-end and imaging applications. Mario Ibrahim, Advanced packaging, technology & market analyst at Yole Développement (Yole) and author of the report 2.5D / 3D TSV & Wafer Level Stacking Technology & Market Updates 2019, had the opportunity to discuss with Paul Enquist, VP 3D R&D at Xperi Corporation.
2.5D / 3D TSV & Wafer Level Stacking Technology & Market Updates 2019 – Yole Développement)
Hybrid bonding technology consists of directly stacking two wafers that have a planarized surface of dielectric with isolated copper interconnections. Hybrid bonding has replaced Through Silicon Via (TSV) interconnections in CIS, where it has reached the break-even point between footprint and TSV savings vs. hybrid bonding process costs. It is now widely used in CIS for premium smartphones by Samsung, Apple & Huawei. Xperi, a technology development and licensing company, has contributed to the development, adoption and implementation of the hybrid bonding process, licensing to major foundries and IDMs their DBI technology.
By 2023, 80% of the CIS production will be based on 3D stacked technology. The market share to be gained by hybrid stacked CIS will rise accordingly, with a CAGR of +43% between 2017 and 2023.
The consumer market, mainly for CIS applications, was in 2018 the biggest contributor to the stacking packaging revenue, with over 65% of the market. Nevertheless, HPC is the application driving innovation of 3D packaging technology and will exhibit the fastest growth up to 2023, with market share doubling from 20% in 2018 to 40% in 2023.
Yole sees further use of hybrid bonding technology for Wafer to Wafer and Die to Wafer, for 3D stacked NAND, 3D stacked DRAM memory and 3D System-on-Chip.
The discussion between advanced packaging experts is reproduced below.
Mario Ibrahim (MI): As a technology development and licensing company, can you briefly introduce Xperi and explain the company’s business model?
Xperi and its subsidiaries (Tessera, Invensas…) have demonstrated a long history of process development including some of the earliest enablers such as the Shellcase, ZiBond and DBI technologies. Can you give us some insights on how Xperi operates and what new solutions Xperi would commercialize? Are you continuing to develop new processes? Do you work jointly with research institutes?
Paul Enquist (PE): Xperi Corporation and its brands, DTS, FotoNation, HD Radio, Invensas and Tessera, are dedicated to creating innovative technology solutions that enable extraordinary experiences for people around the world. Xperi’s solutions are licensed by hundreds of leading global partners and have shipped in billions of products in areas including premium audio, automotive, broadcast, computational imaging, computer vision, mobile computing and communications, memory, data storage, and 3D semiconductor interconnect and packaging. With regard to 2.5D / 3D technology solutions, Xperi is focused on development and commercialization of Invensas ZiBond Direct Bonding and DBI Hybrid Bonding technologies for a wide range of semiconductor applications. We collaborate across the supply chain from materials suppliers and equipment vendors, to semiconductor manufacturers and foundries as well as select research institutes, like Fraunhofer IZM-ASSID.
(Courtesy of Xperi)
MI: 2.5D & 3D stacking technologies are considered two of most promising alternatives to Moore’s law slow down. The stacking revenue (packaging) is expected to exceed $5.7B in 2023. How does Xperi see the future of these integrated solutions?
PE: It’s a very exciting time for the semiconductor packaging industry. With Moore’s Law and node scaling, the historical means of improving performance, functionality, power consumption and cost, largely coming to an end, the industry is increasingly looking toward 2.5D and 3D stacking and integration technologies to meet market demands. Invensas 2.5D and 3D integration technologies allow the semiconductor industry to extend beyond Moore’s Law. This shift can be readily seen by the adoption of Invensas ZiBond and DBI stacking technologies in Backside Illuminated (BSI) image sensors today. Recently, these technologies have enabled submicron pixel scaling and heterogeneous integration of photodiodes, logic, and memory in stacked BSI image sensors. We believe the fundamental cost and performance advantages of our stacking technologies will broadly convey to many other applications. For example, the 3D NAND and DRAM memory markets are well-poised to adopt DBI Hybrid Bonding in the near future.
MI: Xperi is known for licensing the ZiBond and DBI processes. What are Xperi’s key market segments and applications for these processes?
PE: Xperi is focused on further developing and commercializing Invensas ZiBond Direct and DBI Hybrid Bonding technologies for a wide range of semiconductor applications including image sensors, RF, MEMS, 3D NAND, DRAM, and logic in 2.5D and 3D-IC configurations. Ultimately, we see DBI Hybrid Bonding enabling a new wave of semiconductor devices rearchitected with 3D in mind from the start as opposed to simply stacking conventional 2D-architected designs.
ZiBond Direct Bonding has also been deployed in RF devices to transfer CMOS switches from high RF loss native SOI substrates to lower RF loss trap-induced silicon or low RF loss non-silicon wafers. We expect the value and applicability of our ZiBond Direct Bonding technology to increase substantially in the RF space as 5G comes to market with its more demanding requirements.
MI: How do you see the transition from ZiBond using TSV to DBI? Do you see further use of these processes?
PE: For many years now, both ZiBond and DBI have been used to manufacture BSI image sensors. It started with ZiBond being used to stack a photodetector wafer on a silicon handle wafer or on a CMOS logic wafer with a TSV interconnect. TSVs have also been used in conjunction with ZiBond to stack and electrically interconnect CMOS logic and memory wafers prior to photodetector wafer stacking. Stacking with DBI instead of ZiBond has been shown to be very effective at replacing TSVs with a simple pad cut enabling further die shrink and process cost savings. We expect to see a continuous transition towards DBI, particularly in the image sensor space as the industry demands pixel-to-pixel level interconnect. That said, we expect ZiBond and DBI will co-exist for many years to come.
MI: Late in 2018, Xperi announced settlement and new patent license agreement with Samsung. Yole is foreseeing the use of hybrid bonding in 3D stacked memory based on DRAM. Will that open the doors to hybrid bonding in HBM & 3D stacked DRAM markets?
PE: We were very pleased to announce the Samsung agreements and look forward to a mutually beneficial relationship for years to come.
Regarding the use of Invensas DBI Hybrid Bonding for HBM and 3D stacked DRAM, we believe it is an excellent solution, particularly in a die to wafer configuration, as it can enable lower electrical parasitics, lower thermal impedance, more stacked die within the JEDEC height limit, and reduced bond cycle time as compared to thermo-compression bonding. Furthermore, the bonding itself can be performed at low temperature and eliminate the need for underfill which are significant benefits over alternative bonding approaches. We are actively working with customers to demonstrate these benefits and expect commercial products in the near to mid-term.
We also see 3D NAND as a significant opportunity for wafer to wafer DBI Hybrid Bonding. Micron-scale DBI interconnects are an enabling capability for partitioning I/O and memory cells into independently optimized process nodes built on separate wafers then stacked resulting in significant performance, density and cost advantages. This is another area of significant activity for us with near to mid-term commercialization potential.
(Schematics of W2W and D2W DBI Hybrid Bonded Wafers – Courtesy of Xperi)
MI: Besides Samsung, YMTC – a China-based new player in memory – has revealed its Xtacking technology late 2018 (not using TSV). Is DBI and wafer-to-wafer assembly process compatible with NAND wafers?
What are Xperi’s plans in the growing Chinese memory market? Can we expect commercialization soon?
PE: Invensas DBI technology is compatible with both DRAM and NAND wafers. The thermal budget of the bonding process can be limited to 150C which opens up the door to a wide range of applications.
With regard to China, the Made in China 2025 initiative is driving demand for advanced semiconductor technologies in China. As a result, we think the up and coming Chinese semiconductor manufacturers and foundries represent a significant opportunity for 3D integration technologies like ZiBond and DBI. We are working with a variety of players in this rapidly growing market and look forward to commercial products soon.
MI: Scaling and low pitch technology added to low temperature bonding are some of the advantages of hybrid bonding. The very low surface roughness required can be a difficulty/drawback of this technology. Can you please expand on the advantages & drawbacks of hybrid bonding?
PE: Scaling of the interconnect pitch is a fundamental advantage of the DBI technology as compared to other technologies. While the Invensas ZiBond Direct and DBI Hybrid Bonding have tight tolerances when it comes to surface roughness and surface cleanliness, industry-standard submicron feature size damascene processes and cleanroom environments, which have been used to build back-end-of-line multi-level interconnect stacks for multiple generations of CMOS process nodes, have proven to be more than capable of meeting the requirements of these technologies as evidenced by the billions of BSI image sensors that have shipped.
MI: What are the next steps of process improvement?
PE: We are continually involved in process improvement efforts both internally directed and with our customers to address specific needs that arise within particular applications. An area of focus over the past few years has been on die-to-wafer DBI Hybrid Bonding which we see as important for DRAM and heterogeneous logic and memory integration applications. Our efforts have focused on the optimization of dicing, cleaning and high throughput die bonding with significant progress having been made. We are excited about the prospects for this particular approach and the impact it can have on the semiconductor industry.
MI: Wafer-to-wafer alignment accuracy specifications are more demanding due to smaller features. What is doable today in HVM and what is on the roadmap for the coming years?
PE: Production wafer bonding tools today are capable of +/- 250nm alignment accuracy, 3 sigma, and are supporting 3.7um pitch DBI Hybrid Bonding in HVM today. Tool vendors have stated that 100nm and even 50nm, 3 sigma alignment capabilities are on their roadmap and we look forward to leveraging this capability when it is available.
MI: Advanced packaging for high-end segments is diversifying. There is a wide range of advanced packaging technologies using, or not, TSV, among them technologies like Foveros & EMIB from Intel, RDL interposer technology from Samsung, CoWoS, 3D SoC & InFO on substrate from TSMC, and SWIFT (AMKOR).
Do you see them as real challengers to the established TSV-based and wafer-to-wafer technologies available? What is Xperi’s position on these technologies? Will Xperi back any of these technologies?
PE: We expect there to be a wide variety of packaging technologies to choose from as market and application requirements vary quite a bit. The reality is that the industry needs a tool box of packaging and interconnect solutions that it can pull from to address the ever-evolving needs of the market. Although there will likely be some consolidation of the solution set employed as applications mature, we expect a variety of packaging and interconnect solutions will remain for years to come. Another thought to keep in mind is that some of these technologies are complementary, not competitive. For example, DBI is a versatile interconnect solution that can be used in conjunction with a wide range of 2.5D and 3D package assembly technologies.
MI: Yole believes that 3D SoC technology will hit the market by 2019 with TSMC as foundry. Hybrid bonding is in pole position to be the interconnection technology used. Is your technology suitable with memory on logic W2W or D2W stacking?
PE: Invensas ZiBond Direct Bonding and DBI Hybrid Bonding technologies, in both W2W and D2W approaches, are suitable for 3D SoC and memory on logic stacking applications. An early example of this, once again, is the image sensor market where memory has been stacked with logic in 3-layer stacked image sensors with ZiBond providing the mechanical bond and TSVs providing the electrical interconnection. DBI Hybrid Bonding can be readily used to achieve this type of integration as well. The D2W work we are focused on today for 3D stacked DRAM is, in fact, directly relevant to 3D SoCs.
An exciting capability that DBI Hybrid Bonding enables for 3D SoC is the ability to connect each die in the stack at a pitch that rivals the interconnect pitch within a die. This can eliminate I/O interfaces and allow for core level interconnects between die that are comparable to connections within a die. This has positive implications on power, area, and metal layer reduction. A challenge in realizing this new design methodology is overcoming the 2D mentality in the planning process. Planning a device in 3D is an architectural paradigm shift where many 3D SoC advantages can be realized with DBI Hybrid Bonding.
(4 and 8-high Stacked DRAM with DBI – Courtesy of Xperi)
MI: The display and AR/VR/MR markets will require high interconnection density to link the display to its driver. Is hybrid bonding compatible with such markets and applications?
PE: Invensas DBI Hybrid Bonding is also well suited for display and AR/VR/MR markets. A common application to these markets is stacking of an optical emitter array layer on a logic driver array layer which is analogous to stacking of an optical detector array layer on a logic read out array layer for image sensor applications. DBI Hybrid bonding can support interconnect pitches down to one micron which may be required for these applications with current or soon to be available tools. Furthermore, these optical emitter markets often require non-silicon emitter materials like GaN which have significantly different thermal coefficient of expansion than silicon. This can be accommodated with the low thermal budget of the DBI Hybrid Bonding process which is distinct from other bonding technologies with higher thermal budgets that are not able to serve these markets and applications.
MI: Wafer to wafer assembly, and consequently hybrid bonding, is a pure foundry business that has been taken away from OSAT’s advanced packaging revenue. Do you see a move by the OSATs to try to re-position themselves in this field?
PE: The low cost of ownership and high value add of Invensas DBI Hybrid Bonding make it a suitable candidate for OSATs interested in improving their margins and expanding their offerings. In particular, the pending commercialization of D2W DBI Hybrid Bonding will provide OSATs an opportunity to leverage their highly relevant die handling experience and expertise.
Dr. Enquist has over 30 years of experience, over 130 publications and presentations and over 50 issued US patents related to high speed devices and circuits, low temperture direct bonding and 3D integration. He holds Ph.D. and M.S. degrees in Electrical Engineering from Cornell University and a B.S. degree in Engineering from Columbia University. He is an IEEE senior member, member of Tau Beta Pi and Eta Kappa Nu.
As a Technology & Market Analyst, Advanced Packaging, Mario Ibrahim is a member of the Semiconductor & Software division at Yole Développement (Yole). Mario is engaged in the development of technology & market reports as well as the production of custom consulting studies. He is also deeply involved in test activities business development within the division.
Prior to Yole, Mario was engaged in test activities development on LEDs at Aledia. He was also in charge of several R&D advanced packaging programs. During his 5 years stay, he developed strong technical & managerial expertise in different semiconductor fields.
Mario holds an Electronics Engineering Degree from Polytech’ Grenoble (France). He spent 3 apprenticeship years within Imaging Division of STMicroelectronics Grenoble, where he contributed to the test benches park automation within the test & validation team.
2.5D / 3D TSV & Wafer-Level Stacking: Technology & Market Updates 2019
2.5D heterogeneous and 3D wafer-level stacking are reshaping the packaging landscape.