Intel turns to TSMC: another step towards fabless?

The recent news that Intel will turn to TSMC to mass produce CPU products signals a new era in the processor IDM/foundry arena.  The production is slated to start in the second half of 2021 and will cover some of Intel’s low- and mid- tier CPU products. Yole Développement’s report “Computing for Datacenter Servers 2021” and “Processor Quarterly Market Monitor” cover the market space where these events are occurring.  Meanwhile, speculation over Intel’s motivation is rampant, as are theories of what this means for the firm’s long-term strategy.

As foundry technology has moved beyond Intel’s in-house capabilities, Intel has often maintained that the nominal process node (14nm, 10nm, 7nm, etc.) was less important than the holistic performance of the chip itself. This claim is not without merit, as there is little consistency between leading-edge semi manufacturers, making comparison difficult. Case in point: we have seen Intel’s 10nm transistor density was well ahead of the foundries’ 10nm and roughly equivalent to that of TSMC’s 7nm. However, this assertion cannot hold through perpetuity, and this recent announcement from Intel is further evidence that its validity is waning.

The amount of capex invested will need to be massive for Intel to undertake a new process node; this much is not new. Therefore, the chips developed on the new node must provide enough device shrink / performance gain / power consumption benefit to generate a positive ROI. It is expected that Intel has a node in development to accomplish this, at least on paper (or in the lab), but there are probably product lines at the margin for which the economics are not ideal to cover confidently the capital risk. Maybe the yield is not yet there, or perhaps it only looks promising for higher-margin server products, or perhaps they simply do not want to realize all the engineering expenses of designing the full range of product SKUs on production lines that will also require a great deal of capex. By turning to a foundry partner, Intel is decoupling the time-to-market risk of its next line of processors from the execution risk of the next process node, which is essentially the value proposition for semi companies to go fabless.

There is certainly a competitive angle to this move as well.  Intel has had well-publicized problems with CPU shortages in the recent past, contributing to Intel’s loss of market share to rival AMD. The outsourcing of manufacturing will better enable Intel to right-size its production for the market, reducing the opportunity for further share loss. Now that the foundry cost + margin will be part of Intel’s economics on certain products, those products may not be as profitable as they once were, but Intel is calculating that it’s better to lose some margin (i.e. share margin with a manufacturing partner) than continue to lose sockets to its main rival.

To make matters worse for Intel, the timing comes as Intel deals with four new fronts in the competitive landscape.

First, the telecommunications and data center networking market continues to heat up with Xilinx also moving its next-generation FPGAs and configurable SoCs onto the 7nm process and introducing adaptive compute acceleration platforms. Nvidia’s acquisition of Mellanox continues to put pressure on Intel’s networking platforms.

Second, while SoCs based on Arm core IP have struggled to open a front in the compute sector for a decade or more, the recent Fugaku supercomputer based on Arm at the top of the Top 500 Supercomputer list has broken a myth that Arm has no place in high-performance computing. Similarly, Apple’s Arm-based M1 replacement for Intel Core series processors in many Macs in 2020 has shattered the barrier for Arm Core IP competing with x86.

Third, integrated graphics and applications processors have been driving smartphones & tablets and other adjacent markets whereas they now encroach on the compute space. AMD and Nvidia continue to drive the importance that graphics have become to the ecosystem, but Intel has been well behind in advanced graphic support until recently. While it is great that Intel is finally releasing Xe, it becomes yet another front in the competitive landscape competing with AMD and Nvidia with the possibility of losing credibility if Xe turns out to be a non-competitive solution.

Finally, and possibly most importantly, Intel has been competing with Nvidia to insert itself as the de facto artificial intelligence platform, but that market is seeing tremendous demand and diversity developing.

From high-end AI accelerator coprocessors to SoCs with AI integrated subsystems and even lowly microcontrollers integrating AI acceleration, the assertion that AI requires high-performance CPUs and GPUs is crumbling as well. While most AI is still processed in data centers on Xeon processors, and Intel continues to expand its support for AI with Movidius, Habana, and Alterra FPGAs, the diversity of this competitive landscape is enormous, and the number of competitors is increasing rapidly. While Intel has the resources to offer powerful synergies with its wide range of processing solutions, the challenge of maintaining its leading-edge manufacturing while expanding into new complex heterogeneous platforms as the market seems to demand may have recently had Intel struggling to allocate its resources.

It is now clear that Moore’s Law is slowing down, if not already dead.

The design cost has risen many times and SoC manufacturing has become extremely complex, leading to an increase in time to market. The way now is to design & manufacture the latest SoC using SiP and chiplet based approach by leveraging different advanced packaging technologies and a mix of both latest & mature nodes. This will reduce the cost and time to market while at the same time enhance the system performance.

Advanced semiconductor packaging is seen as a way to increase the value of a semiconductor product, adding functionality, maintaining/increasing performance while lowering cost. Intel has realized the significance of advanced packaging and invested heavily in it in the last 3-4 years.

Intel, who are the pioneers of Moore’s Law and mainly relied on front-end scaling for performance improvements, is increasingly looking at heterogeneous integration using advanced packaging technology to complement their front-end effort. Advanced packaging is migrating from the substrate platform to the wafer/ silicon level and Intel has emerged as a key player in this domain, like TSMC. Intel’s Advanced packaging vision is to develop and own leading-edge technology to connect chips and chiplets in a package to match the functionality of a monolithic SoC. High density interconnects that enable high bandwidth at low power is essential to realize this vision. Traditionally Intel has been at the forefront in implementing many packaging technologies, such as the industry’s first organic flip-chip substrate, wider adoption of Cu pillar bumping, thermo-compression bonding, etc. However, Intel is entering into a new era with the introduction of high-end advanced packaging technology – EMIB, Foveros & Co-EMIB architectures – with internal investment in manufacturing. Intel’s advanced 3D IC architectures will target initially mobile products such as tablets, while also offering high-end solutions for HPC and 5G eco-systems. Intel continues to advance in chiplet based architecture approach as well as using Foveros, & Co-EMIB architectures and developing high-density interconnects using hybrid bonding technology as a tool for heterogeneous integration.

As for what this means for Intel’s long-term strategy, the results could land in a range of possibilities depending on the success of Intel’s next process node. This could be just a stop-gap contingency, where Intel pulls the manufacture of these product lines back in-house once there is more confidence and stability in process node development. 

Alternately, this may be the beginning of a long march toward Intel becoming one of many fabless semiconductor companies.  It’s the opinion of this author that the long-term strategy will be one of a hybrid: wafer processing is kept in-house for many Intel products, using Intel-developed process technology to do so, but the relationship with foundries will be maintained for a portion of the product line allowing Intel to be more nimble with its production. A byproduct will be this new competitive dynamic where Intel and AMD compete not just for CPU sockets and design wins, but for foundry capacity as well; TSMC should be pleased with that.

About the authors

Tom Hackenberg is a Principal Analyst for Computing and Software in the Semiconductor, Memory and Computing Division at Yole Développement (Yole). Tom is engaged in developing processor market monitors and research into related technology trends. He is currently focused on low and ultralow power solutions such as MCUs. Tom is an industry leading expert with more than a decade’s experience reporting on markets for semiconductor processors including CPUs, GPUs, MPUs, MCUs, SoC ASICs & ASSPs, FPGAs and configurable processors. Tom is also well-versed in related technology trends including IoT, heterogeneous processing, chiplets, AI and edge computing.

Prior to joining Yole, Tom was a principal analyst at OMDIA, IHS Markit and began processor market research in 2006 for IMS Research. He worked with market-leading processor suppliers developing both syndicated and custom research. Tom holds a BSECE from the University of Texas at Austin specializing in Processors and FPGAs.

Santosh Kumar is currently working as Principal Analyst and Director Packaging, Assembly & Substrates for Yole Développement’s activities in Korea. Based in Seoul, Santosh is involved in the market, technology and strategic analyses of the microelectronic assembly and packaging technologies. His main interest areas are advanced IC packaging technology including equipment & materials. He is the author of several reports on fan-out / fan-in WLP, flip chip, and 3D/2.5D packaging.

Santosh Kumar received the Bachelor’s and Master’s Degree in Engineering from the Indian Institute of Technology (IIT), Roorkee and University of Seoul respectively. He has published more than 40 papers in peer reviewed journals and has obtained 2 patents. He has presented and given talks at numerous conferences and technical symposiums related to advanced microelectronics packaging.

John Lorenz is a Technology and Market Analyst within the Computing & Software division at Yole Développement (Yole), part of Yole Group of Companies.  John is engaged in the development of market and technology monitors for the logic segment of advanced semiconductors, with an initial focus on processors.  Prior to joining Yole, John held various technical and strategic roles at Micron Technology.

On the engineering side, his roles included thin film process development and manufacturing integration on DRAM, NAND, and emerging memory technologies and industrial engineering / factory physics for the R&D fab. 

On the strategic side, John ran the memory industry supply & capex model for corporate strategy / market intelligence and established the industry front-end costing model within strategic finance.

John has a Bachelor of Science degree in Mechanical Engineering from the University of Illinois Urbana-Champaign (USA), with a focus on MEMS devices.

This article has been done in collaboration with Emilie Jolivet, Director of the Semiconductor, Memory & Computing Division and Adrien Sanchez, Technology & Market Analyst, Computing at Yole.

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Source: http://www.yole.fr,

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