Description Fan-Out and Embedded Die: Two promising Wafer/Panel-Level-Packaging technologies. What are the next steps for the growth?Fan-Out Wafer Level Packaging is already in high-volume – but it’s about to grow even more strongly
Fan-Out Wafer Level Packaging (FOWLP) started volume commercialization in 2009/2010 and started promisingly, with initial push by Intel Mobile. However, it was limited to a narrow range of applications – essentially single die packages for cell phone baseband chips – reaching its limit in 2011. In 2012 big fab-less wireless/mobile players started slowly volume production after qualifying the technology.
It faced strong competition from other packages such as wafer-level chip scale packaging (WLCSP) in 2013/2014. Intel Mobile also backed off from the technology, and the main manufacturers reduced their prices in 2014, creating a transition phase with low market growth.
As shown in figure 1, we now expect strong growth. Today, the market is worth almost $200M and we anticipate 30% CAGR is in coming years. One of the key factors driving this is the arrival of 2nd generation FOWLP. More customers are also being convinced, a wider range of potential applications reached, and technology qualifications started during the transition phase completed by strong fabless players.
What can explain such great potential?
This question is investigated in detail in the report. Primarily, mobile customers have high expectations of miniaturization and higher integration while keeping costs low. This leads naturally to WLP for cost and performance and system-in-package (SiP) solutions for integration and functionality. FOWLP has proven its ability to reach these targets. Its small form-factor and low cost potential shown in the 1st generation are now enhanced with high-integration capability of the 2nd generation as shown in figure 2.
Benefiting from the delay in introducing 3D through-silicon via (TSV) architectures, FOWLP is currently seen as the best fit for the highly demanding mobile/wireless market and is attractive for other markets focusing on high performance and small size. In this report, we provide a complete overview of the different market expectations and a detailed application-by-application breakdown.
High market potential also means strong interest among manufacturers and a lot of innovative technologies are already available or currently under development. This report describes the different strategies and products of each player involved in FOWLP, from the main outsourced assembly and test companies, like STATS ChipPAC and Nanium, to foundries like TSMC.
This report also provides detailed roadmaps and supply chain analysis, explaining the complexity and the trends already showing potential in this highly promising market.
Since cost is always the first driver, the report also focuses on equipment and material challenges and substrate size evolution, both for wafers and panels.
Embedded Die in Substrate packaging’s promise faces challenges
Similarly to FOWLP, Embedded Die in Substrate is an approach getting the attention of potential customers, as it brings many advantages. The embedding allows a smaller form-factor, and it can be done using a mature manufacturing chain, providing low costs. The approach also offers good thermal performance, high integration capability and low inductance thanks to shorter connections.
But these advantages still have to be realistic at high volume manufacturing scales before being able to convince customers. Embedding die in laminate substrates is indeed a promising packaging principle, but it has to overcome several challenges.
The first one is the supply chain. The process is being pushed by printed circuit board manufacturers such as AT&S and can create a new supply chain, bringing new players into the semiconductor industry. This new supply chain comes along with new business models, like those described in figure 4.
One of the supply chain’s main advantages is the usage of a mature and affordable manufacturing chain created initially for PCB manufacturing. That achieves low cost technology that would allow easier component integration, with easy access to both sides of the chips. However, a new supply chain brings with it a lack of technical experience with embedding processes and questions about business models that require clarification.
This report gives an overview of players involved in embedded die packages. It describes the strategies they’re hoping will overcome technical issues such as yield, resolution and reliability and their choices of business model to enter the semiconductor packaging market with.
A special focus is made on markets of interest, describing which applications will drive the embedded die market in the future and the potential reasons for success. Single die are the first products currently being sold, demonstrating the technology’s capabilities. They are essentially low I/O applications with easy to embed dies such as DC/DC converters for wireless products. Our expectations are that the technology will show its real potential with more complex systems such as power application SiPs. There, actives and passives will fully benefit from embedded packages thanks to good heat management and low inductance.
This report details the different milestones this technology must pass if it is to reach high volumes, and what room there is for innovations where embedded die could provide clear added value.
The report also describes the different possibilities under investigation or required by customers to achieve volume manufacturing and sustainability. These include details of technical requirements, multi-sourcing and standardization needs and integration roadmaps.
Among the technical requirements, one is especially important: pad pitch on the die. In order to reach volume in the mobile/wireless market, pad pitch has to go below 150 µm. Some players, like TDK-EPCOS, claim they already have products with 50 µm pitch.
If technical and logistic objectives like this are achieved, and if an application provides a real boost in terms of initial large volumes, the overall market will be able to grow rapidly in the near future. This is described in figure 1.
What’s new compared to last edition?
- Overview of Fan-Out and Embedded Die technologies available and under development
- Commercialization status, market adoption and potential analysis update per technology
- New players in the market analysis. For FOWLP that includes SPIL, TSMC, Deca Technologies, etc... For Embedded Dies, it includes Unimicron, Schweizer, etc…
- Updated market sizes and split per application
- Market adoption roadmaps
- Panel and wafer volume forecasts
- Roadmap of panel adoption and panel equipment readiness