At the recent ECTC Conference in Las Vegas start-up X-Celeprint presented 4 papers on their Micro-Transfer-Printing, μTP, process and how it can be applied to various aspects of microelectronics. The μTP technology is an advanced assembly technology which allows the accurate movement of hundreds of small (sub mm is their sweet spot) devices at a time. I-Micronews.com thought it was worth… a closer look.
X-Celeprint is a wholly owned subsidiary of XTRION N.V. which also includes well known X-Fab. They licensed the technology from Semprius and began operations in early 2014. Micro transfer printing was originally invented by Professor John Rogers at University of Illinois – Urbana Champaign and developed by Semprius Inc.
Micro-Transfer-Printing (μTP) in its simplest description, uses engineered elastomer stamps coupled with high-precision motion controlled print-heads to selectively pick-up and print (place) large arrays of microscale devices onto alternative substrates. The devices (chiplets) are first fabricated on a “source” wafer, and then “released” by removing a sacrificial layer that exists underneath the semiconductor circuit. A microstructured elastomeric stamp (designed to match the source wafer) is then used to “pick up” and “print” the devices onto a target substrate.
The ability to selectively tune the adhesion between the elastomer stamp and the printable device by varying the speed of the print-head controls the assembly process. When the stamp is moved quickly, the adhesion is large enough to “pick” the printable elements away from their native substrates, and conversely, when the stamp is moved slowly away from a bonded interface the adhesion is low enough to “let go” or “print” (i.e place) the element onto a receiving surface.
The process is massively parallel in that the stamp can be designed to transfer thousands of discrete devices in a single pick-up and print operation. For instance if 240 um sq. chips are laid out on a wafer at 250 um pitch and they need to be placed onto a new surface at 2 mm pitch then the stamp will be made up so that the stubs on the stamp (see transfer print stamp below) are at 2 mm pitch and therefore pick up chiplets 1, 8, 16 etc. off the wafer and then come back for chiplets 2, 9, 17 etc.
Micro Transfer Printing process: (A) Elastomer stamp approaches wafer; (B) elastomer stamp picks up chiplets; (C) elastomer stamp approaches substrate; (D) stamp “prints” (places) chiplets on substrate (Source: X-Celeprint)
They have examined a wide variety of printable microscale devices, including lasers, LEDs, solar cells, and integrated circuits in a variety of IC materials including silicon, GaAs, InP, GaN and thin-film dielectrics including diamond.
In most cases the devices to be transfer printed first go through a process to release them from their source wafer. This method utilizes sacrificial release layers underneath the device layer. In the case of silicon devices, silicon-on-insulator (SOI) wafers represent a convenient and readily available source wafer. Circuits are fabricated, using a commercially available SOI CMOS foundry process with a 5 um device silicon layer and a 1 um buried oxide.
Following the foundry CMOS process, a trench is cut down to the device silicon around the periphery of the device. An encapsulation layer is then applied to the SOI CMOS source wafer to protect the ILD and wiring levels during the subsequent BOx etch. The SOI CMOS wafer goes through the etch process to remove the BOx underneath the devices with HF. The devices are now completely free from the handle wafer, but held is place using tethers in the device layer. The tethers are designed to break or cleave in a controlled manner during transfer printing. Following the sacrificial etch process the encapsulating layer is removed at which points the ICs are ready for transfer-printing.
Fabrication of devices for transfer printing: (A) SOI wafer following foundry fab; (B) formation of trench and encapsulating layer; (C)trenching through device silicon and removing buried oxide (Source: X-Celeprint)
In the 2016 ECTC paper “Heterogeneous Integration of Microscale Gallium Nitride Transistors by Micro-Transfer-Printing” X-Fab author Ralf Lerner detailed the process for GaN chiplet formation as shown below.
The process flow for heterogeneous integration of GaN HEMTs: (a) transistors are fabricated on Si wafer; (b) Devices are isolated, passivated and undercut; (c) Devices are lifted on elastomer stamp; (d) The devices are printed to CMOS wafer and interconnected using thin-film Al traces. (Source: 2016 ECTC)
The gallium nitride transistors are fabricated on 100 mm diameter, <111> silicon wafers. The individual devices are isolated by reactive ion etching (RIE) through the device layers down to the underlying silicon substrate. A silicon dioxide hard mask is used in this step. A 600 nm layer of silicon nitride is deposited by plasma-enhanced chemical vapor deposition (PECVD). This silicon nitride layer passivates the sidewalls of the device and also serves to form the anchor and tether structures.
The GaN chiplets are transferred onto a Si CMOS wafer. A thin semiconductor grade planarizing resin is applied to the CMOS wafer before printing. After the micro-transfer-printing is complete, the underlying resin is cured at 175 °C. Next, the interconnections are formed by sputter depositing a metal stack of TiW and Al followed by subtractive wet-etching. The printed GaN HEMT chiplets are ~ 5 μm thick, and the sputtered Al does an effective job at routing up the device sidewall. SEMs of the interconnected GaN HEMTs are shown in figures below.
Interconnected GaN HEMT: (A) Al wiring routing up the sidewall of the transfer-printed GaN HEMT; (B) expanded view (Source: 2016 ECTC)
In the paper “Fan-Out Packaging of Microdevices Assembled Using Micro-Transfer-Printing” researchers at X-Celeprint and RTI Int. described a high throughput strategy for making fan-out packages for sub-millimeter, devices which do not require molding compound. Micro-transfer printing was used to assemble reconfigured wafers of devices (80um x 40um chips with a redistribution metal and six contact pads), face-up, onto 200mm wafers. After assembly, they undergo a standard wafer level redistribution and bumping process. The final fan-out package pitch on the 200 mm wafer is 1.4mm x 1.0mm with six 250 μm solder bumps. The fan-out packages were assembled and reflowed onto FR4 test boards.
Since no molding compound is used the packages do not suffer from die drift which normally occurs during compression molding.
The transfer printing process was estimated to have a 99.7% yield and was used to transfer 300 chiplets every 30 seconds.
FOWLP fabricated by µTP: (A) Chiplet source wafer after partial removal; (B) Completed fan out package before solder ball placement; (C) Close-up; (D) Final FO-WLP
Two PCBs populated with 60 die each were put into thermal cycle testing using JESD condition G, -40°C to 125°C. None of the die showed more than 0.2 ohm change in average resistance.
Phil Garrou for Yole Développement
Related Reports and Monitors
Advanced packaging technology in the Apple Watch Series 4’s System-in-Package
Reverse Costing - Structural, Process & Cost Report
ams Ambient Light Sensor with WLCSP TSV Packaging
Reverse Costing - Structural, Process & Cost Report