The purpose of this article is to provide insight into why Deca’s Fan-Out Technology has recently been adopted by Qualcomm as a protection layer for its PMIC Fan-in Wafer-Level-Packaging (WLP) die. It can be argued that this is still strictly a Fan-In die with side-wall passivation done by Fan-Out Packaging. Hence, the first portion of this article will describe the Fan-In WLP market and the various challenges faced by this technology for thinner die applications. The second part of this article will highlight how Deca’s differentiated Fan-Out Technology is being adopted as the solution amongst other packaging options.
In recent years, demands for Fan-In WLP have been extraordinary, fueled by the tremendous driving force of smartphone functionalities, such as PMIC, WiFi/BT combo, Transceivers, Image sensors, Analog/Digital functions etc. Presently, the Fan-In WLP market is expected to grow steadily from $2.9B in 2018 to $4.4B in 2024, at 6.5% CAGR (Source: Fan-Out Packaging: Technologies and Market Trends report, Yole Développement, 2019)
Fan-In WLP package typically undergoes full function test at wafer level followed by mechanical blade dicing. However, mechanical blade dicing may cause either front side chipping or backside chipping, which results in yield issues that are not detected before the SMT process. Besides, with thinner profile requirements, one of the key trends in consumer products, the die is more brittle mechanically. This generates a new challenge for supply chain players in general.
As thinner Fan-In WLP dies ramp up to high volume manufacturing, this yield-loss can no longer go unaddressed because the cost is increasingly sensitive with production maturity. Fabless players are wary of such potential failures and have actively started seeking for a solution. Industry players are looking to improve the current process for better performance and enhanced board level reliability, essentially by providing side-wall protection for the bare Si die nature of Fan-In WLP. Equally important, the infrastructure has both 200mm and 300mm wafers supporting Fan-In WLP production. Hence, this solution must be able to manage and process dies regardless of the original wafer size. Extending beyond Fan-In WLP, Fan-Out Packaging, which fulfils all the requirements, has been assessed as one of the top options and was eventually adopted as the technology to resolve these major challenges.
Qualcomm has been engaged with OSATs to improve the PMIC side-wall protection by Fan-Out Packaging. For the first time ever, Qualcomm has switched from ASE’s to Deca’s Fan-Out technology, M-Series™, for the processing of side-wall protection around PMIC Fan-In WLP die. Although it is Deca’s M-Series, the processing is still manufactured by ASE. Deca’s M-Series is a rugged, fully molded fan-out, wafer-level chip-scale package (WLCSP) technology that provides high reliability. In the case of Qualcomm’s PMIC, Deca’s M-Series provides a 4-side molded protection which can address sidewall cracking of the die. Due to cost considerations, protection against backside chipping is not processed. Qualcomm’s new PMIC qualification by Deca’s M-Series is being adopted in the latest Samsung Galaxy S10 (Qualcomm Snapdragon version 855), which is unprecedented.
Deca’s M-Series has been selected by Qualcomm as the encapsulation technology for PMIC dies due to its superior reliability in BLR and better results in crack and drop tests, etc. M-Series is a Chip-First Face-Up process with a natural additional layer of EMC between Solder and Die. This can also be viewed as a stress buffer layer which enables bigger solder balls to be placed at finer pitch, providing significantly higher reliability. Furthermore, properties of M-Series EMC are optimized, and its mechanical performance is similar to the likes of IC Substrate laminate in FC CSP, which is impressive.
This Deca new business win for M-Series technology is sending out a strong signal to competitive technologies, causing a ripple effect throughout Fan-Out supply chain. It is understood that the BLR performance of the M-Series is about 3x better than eWLB and Fan-In, and within a comparable range of thick and thin FC CSP. There are four significant reasons. Firstly, the industry has established Fan-Out Packaging as the preferred technology over Fan-In WLP bare Si die since dicing will cause chipping and it is exacerbated by thinner dimensional criteria. Secondly, within Fan-Out Packaging technologies, the most prevalent eWLB which is licensed and used by many big players, such as ASE, Amkor Portugal (former Nanium) and JCET Group (former StatsChipPAC), is not the automatic choice because it is a Chip-First Face-down process. This process flow does not have an additional layer of EMC between die and solder which is the enabler for better BLR performance. Thirdly, although FC CSP is comparable to M-Series for BLR performance, in mobile applications the trend is to go thinner, so FC CSP loses its appeal due to extra thickness of the IC substrate laminate. It is understood that M-Series can even exceed the BLR performance of thin FC CSP. Finally, value-for-money. Even though Deca’s M-Series ASP is higher than eWLB and twice that of Fan-In WLP, the yield-cost gain due to improved reliability and quality far exceeds the higher margin in M-Series ASP. Deca’s M-Series customer traction is due to its technical value, not cost reduction.
Separately, M-Series process flow and final structure were compared with TSMC inFO since both are Chip-First Face-Up, although these two technologies serve in different market segments and device domains. It is noted that TSMC inFO does not have that additional layer of EMC as in Deca’s M-Series, with TSMC only having PBO film between die and solder. Also, TSMC inFO Cu stud is shorter than Deca’s M-Series with an additional layer of Cu RDL. It is believed that TSMC is trying to compensate for the limited resolution of lithography with a larger Cu RDL via, unlike Deca’s proprietary Adaptive Patterning™, a process that was developed to overcome the die-shift problem, where RDL via is in line with Cu Stud by +/- 0.2um.
The most popular benefit of Fan-Out Packaging is the increased I/O area beyond die limit integrating dies together flexibly, all done at a thinner thickness profile. Clearly, established Fan-Out packaging solutions like eWLB and inFO will continue to focus on “Fan-Out” of I/O. On the other hand, Deca’s M-Series provides a reliable solution as side-wall protection to Fan-In Die, which is a new benefit. Such an approach represents a distinctive differentiation from the traditional Fan-Out Packaging market and helps to address many of the manufacturability, cost, yield, and reliability issues. To sum up, Deca’s M-Series has made an impressive breakthrough within Low-Density Fan-Out Packaging or Core Fan-Out market.
About the authors:
Favier Shoo is a Technology and Market Analyst in the Semiconductor & Software division at Yole Développement, part of Yole Group of Companies. Based in Singapore, Favier is engaged in the development of technology & market reports as well as the production of custom consulting.
After spending 7 years at Applied Materials as a Customer-Application-Technologist in advanced packaging marketspace, Favier had developed a deep understanding of the supply chain and core business values. Being knowledgeable in this field, Favier had given trainings and held numerous technical review sessions with industry players. In addition, he had obtained 2 patents.
Prior to that, Favier had worked at REC Solar as a Manufacturing Engineer to maximize production capacity.
Favier holds a Bachelor in Materials Engineering (Hons) and a Minor in Entrepreneurship from Nanyang Technological University (NTU) (Singapore). Favier was also the co-founder of a startup company where he formulated business goals, revenue models and marketing plans.
Stéphane Elisabeth, PhD has joined System Plus Consulting’s team in 2016. Stéphane is Expert Cost Analyst in RF, Sensors and Advanced Packaging. He has a deep knowledge of materials characterizations and electronics systems.
He holds an Engineering Degree in Electronics and Numerical Technology, and a PhD in Materials for Microelectronics.
Santosh Kumar is currently working as Principal Analyst and Director Packaging, Assembly & Substrates, Yole Korea. Based in Seoul, Santosh is involved in the market, technology and strategic analysis of the microelectronic assembly and packaging technologies. His main interest areas are advanced IC packaging technology including equipment & materials. He is the author of several reports on fan-out / fan-in WLP, flip chip, and 3D/2.5D packaging.
Santosh Kumar received the bachelor and master degree in engineering from the Indian Institute of Technology (IIT), Roorkee and University of Seoul respectively. He has published more than 40 papers in peer reviewed journals and has obtained 2 patents. He has presented and given talks at numerous conferences and technical symposiums related to advanced microelectronics packaging.
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