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Advanced Packaging

Yole Développement is pleased to have interviewed Dr. Choon Heung Lee, Executive Vice President for Worldwide Manufacturing at Amkor and President of Amkor Technology Korea about fan-in wafer level packaging (WLP). Amkor is one of the leading fan-in WLP manufacturers today. The fan-in WLP market is forecasted to grow to $8B by 2020, while current demand is outweighing capacity. Learn more by reading the following interview, and then discover Yole Développement’s new report, Fan-in Wafer Level Packaging: Market and Technology Trends.


Yole Développement: As one of the leading manufacturers of fan-in WLP, can you explain how Amkor is ChoonHeung Amkorpositioned in this sector?

Choon Heung Lee: Amkor has been running fan-in WLP for more than ten years with several structures and applications. Amkor has manufacturing facilities in Korea, Taiwan and China and provides timely support to the market through major foundries. Each country can offer full turn-key solutions including bump, test and backend die processing services (DPS). Amkor has developed various fan-in WLP technologies based on every conceivable customer and market requirement, including thinner structures, new materials, improved board-level reliability performance and large die solutions.

YD: How important is fan-in WLP for Amkor’s business, currently and in the future?

CHL: In the past four years, Amkor’s bump and fan-in WLP capacity has doubled, driven by mobile applications. We are expecting more growth of fan-in WLP thanks to the ‘internet of things’ (IoT), and now our new K5 plant is under construction in Korea for advanced through-silicon via and bump technology. Amkor also plans to expand our capability again, and this will help advance the fan-in WLP business further.


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YD: Which applications are currently driving fan-in WLP and which other applications do you see adopting fan-in WLP in the future?

CHL: Currently the major applications for fan-in WLP are mobile-based power-management integrated circuits (PMICs), power amplifiers (PAs), near-field communication (NFC), e-compass, radio-frequency (RF) connectivity, audio, and some analog devices like switches and drivers. In the future, we think, the same applications will remain important, but high in/out (I/O) count and large body applications will be increasing. MEMS or sensors using fan-in WLP technology will also be  introduced and grow as the IoT and wearable markets emerge.

YD: For these applications, what are the main advantages of fan-in WLP compared to other packages?

CHL: The strongest driving factors for fan-in WLP are cost and form factor in the mobile area.

YD: What are the main fan-in WLP technical challenges and how is the industry, and Amkor specifically, addressing them?

CHL: There are several technical challenges, like board level reliability performance for large dies, chipping and cracking after sawing, and I/O counts being limited by package size. For large die fan-in WLP, we are developing new passivation materials and new solder alloy technology to improve board level reliability. To reduce chipping and cracking, we have developed another dicing technology like plasma dicing and stealth dicing. For the I/O count limitation, Amkor has already qualified 0.3mm pitch fan-in WLP to accommodate more I/Os within a die.

YD: What are today the most advanced features required for fan-in WLP packages? How is Amkor positioned to address them?

CHL: As greater I/O counts are required, line width and space (L/S) should be reduced, while ball count is increasing and ball pitch is decreasing. Now Amkor can achieve L/S below 5µm and three redistribution layer (RDL) fan-in WLP has been in production for a while. The market currently requires total thickness below 300µm, including bump, even below 200µm for the wearable market. Amkor is focusing on new processes and material development, like tape-through marking, wafer mount tape and a back-grinding (BG)/saw process.



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YD: Most manufacturers refer to two RDL configurations as a new option in the high volume fan-in market, with three RDL not in the high volume manufacturing (HVM) plan yet. Which applications might need three RDL fan-in and is this indeed in HVM?

CHL: It’s not in HVM. If three RDL is needed, that might not be for I/O connection but for electrical requirements like ground/RF functions. We think this will remain a very specific area.

YD: Is it possible to provide any more explanation and information about the advantages and technical characteristics of your new process steps and materials like tape-through marking, wafer mount tape, and the BG/saw process?

CHL: Tape-through marking provides a thin wafer handling advantage during laser marking. The wafer mount tape work provides a 2-in-1 tape, combining wafer mount tape and backside lamination film, minimizing the number of process steps. The BG/saw process involves plasma dicing from thin silicon, small die and narrow saw street designs

YD: One of the main advantages of fan-in WLP is low cost, however, the market is continuously pushing for further cost reductions. What are the main initiatives Amkor and the industry is taking to further reduce the cost?

CHL: Amkor has been developing new processes and materials, especially in the photo process area to further reduce costs. New re-passivation materials like epoxy mold compound (EMC) have already been developed, and a direct laser patterning technology can reduce the number of process steps in the photo loop. And we can consider 2L mask fan-in WLP for specific applications and areas like smaller die size and lower ball counts.

YD: Can you please clarify if you are referring to EMC as RDL dielectric material? Is there a limitation for mold compound-based materials as RDL dielectrics for sub 10µm L/S? Are liquid crystal polymers (LCP) one of the possible options for mold compound based RDL dielectric?

CHL: Yes, It's a replacement for polyimide/polybenzoxazole repassivation layers. EMC material is not directly related to L/S, warpage performance is more important. We haven’t considered LCP material so far.

YD: Is it possible to provide any more explanation and info on the laser patterning technology that helps to reduce the number of process steps in the photo loop?

CHL: It’s direct patterning on the passivation layer, which can skip align/exposure, develop and mask design/tooling.

YD: In some cases, fan-in WLP dies are enclosed in a thin protective layer, based on a panel type process. How significant is fan-in WLP encapsulation and can fan-in WLP benefit from panel manufacturing?

CHL: If you are talking about panel level fan-out package, the structure and encapsulation has been developed successfully, but there is still a yield and cost concern.

YD: We have seen fan-in dies that have a very thin mold compound, around 30µm or so. Do you see advantages in thin-molding the fan-in die? If so, for which applications? Can it possibly become more popular as it's based on a fan-out panel process that might come strong in the near future?

CHL: We think it is only for side chipping protection purpose. It strongly depends on the customer's chipping requirement. We think that the market needs more time to compare the improved chipping level and increased cost and time for average turnaround (TAT). So far, there is no strong demand or movement.

YD:  Through our studies we found out that demand for Fan-in WLP is higher than today’s capacity, for both 200mm and 300mm.  Do you agree with this statement? If yes, what are the main applications driving this increase in demand?

CHL:  I agree. The mobile market is still the main driving application, including the IoT market. Small die size and small I/O analog applications can also drive smaller form factors and low cost.

YD:   What the assembly fab utilization rate and most importantly how will the extra needed capacity be added?

CHL:  We think fan-in WLP utilization is quite high nowadays, generally above 85% on average worldwide, but today’s mobile market requests shorter TAT and readiness for peak demand fluctuation. Outsourced semiconductor assembly and test providers (OSATs) need to consider not only increasing capacity but also how to improve productivity and equipment utilization and flexibility.

YD:   Who is most likely to lead expansion, OSATs, bumping houses, integrated device manufacturers or foundries?

CHL:  OSATs and bumping houses.

YD: What is the range of investments needed for a fan-in WLP line?


CHL:  It’s not easy to define it at this time. Fan-in WLP will have an advantage, but we are not sure if the market will accept the higher cost. On average, $35M of investment per module is needed.

YD:   How can OSATs compete against Chinese capital as well as foundries like TSMC entering the WLP market?

CHL:  Amkor can continue to lead in more advanced technology and structures to meet customer requirements in a timely way. Also our full turnkey experience and capability, including WLP, test, DPS and assembly should be a strong point.

YD:   As the Internet of Things is expected to grow in coming years, turning into the next market driver, many discussions are taking place today regarding the packaging technologies that will grow to support IoT. How do you see the packaging landscape driven by IoT?


CHL:  The main application areas of IoT will be MEMS, sensor and connectivity, so we think quad flat no-leads (QFN), fan-in WLP and system-in-package (SiP) will be the package platforms with the greatest prospects for IoT.

YD:   Do you see certain packaging platforms, such as fan-in WLP, fan-out, SiP or flip chip, as having an advantage over the others?

CHL:  Fan-in WLP has a benefit in terms of small footprint and low cost. SiP also has an advantage in terms of providing multi-functional modules for a certain applications.

YD: The need to incorporate more functionalities within the package will drive the need for more integrated packages rather than discrete ones. Do you think SiP could disrupt the fan-in market and supply chain?  Electronic manufacturing services (EMS) organizations are also positioning themselves to support SiP manufacturing. We have seen foundries entering packaging, will EMS also become a threat to OSATs given their low production costs and operating margins?

CHL:  SiP will grow more as one of the main packaging platforms, especially for IoT applications. Otherwise, there will be no big change. OSAT will keep supporting both discrete package and SiP, and EMS will be more specialized in very specific design requirement areas.

YD: Contrary to general trends of package miniaturization, we have seen increases in package size for fan-in WLP in order to accommodate more I/Os. However this also becomes a limitation from the warpage point of view. The fan-out platform is well positioned to accommodate more I/Os, therefore, do you think fan-out could take market share away from fan-in or do you see fan-out as a complementary packaging technology?

CHL:  We think that the market hasn’t decided yet because fan-out packages are still only in niche markets. Customers are also considering reducing fan-in WLP ball pitch, while lead-frame package and single layer substrate technology can compete with the fan-out area. Fan-out will not replace fan-in, but the fan-in market will still be there because of the form-factor and die size limitations and the fine ball pitch solution. Some areas such as multi chips and RF connectivity combo chips will be considered as fan-out first.


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YD: Do you see any other packaging platform taking market share from fan-in WLP?       

CHL:  Panel level packaging still has limitations and challenges on yield, cost and infrastructure.

YD: What is Amkor’s strategic focus for the future and how does fan-in WLP fit into that?

CHL:  To expand the applications conventional fan-in WLP can address we are focusing on low cost fan-in WLP development and large die size fan-in WLP development. Also we are developing more advanced wafer level processing for the future high performance fan-in WLP, for example finer L/S. Fan-in WLP is the most important priority for Amkor. The top three packages for current smart phones are fan-in WLP, flip-chip chip scale packages (FCCSP) and lead-frame packages. Lead-frame packages are already mature, and FCCSP has exploded. But fan-in WLP is still a growing and emerging area. IoT and MEMS will be strong driving forces for the fan-in WLP market.

ChoonHeung Amkor
ChoonHeung joined Amkor in 1996 as the Team Manager of the Simulation and Advanced Product Development group. In 2010 he was promoted to Head of Corporate Technology, and in March 2015, Choon was promoted to President of Amkor Technology Korea.  Choon has written 23 research papers on various packaging technology related subjects and has been granted 26 patents in Korea and 11 in the US.  Choon holds a degree in physics and a Masters degree in statistical physics from Korea University and a Master’s Degree and Ph.D. in semiconductor physics from Case Western Reserve University.

More information about Fan-in Wafer Level Packaging: Market and Technology Trends report

Source: www.amkor.com - www.yole.fr

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