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Advanced Packaging

With FOWLP adoption spreading from mobile/wireless and automotive to MEMS, RF SiP, and medical, a wealth of lucrative business opportunities exist for fan-out equipment and materials suppliers. According to Yole Développement analysis “Equipment and Materials for Fan-Out Packaging”, the total FOWLP equipment market is expected to reach about US$694 million in 2021 at an impressive CAGR of 42.5% between 2015 and 2021. 

However the challenges and market landscapes are very different from process step and the market is quite diversified. Yole Développement interviewed David Butler, EVP and General Manager of SPTS Technologies Ltd., an Orbotech company, about his vision of the market and company’s solutions.

FOWLP equipment market forecast Yole report

(Source : Equipment and Materials for Fan-Out Packaging, March 2017, Yole Développement)

Yole Développement: Can you present SPTS and its solutions, in particular in the PVD activities?

David Butler: SPTS is a manufacturer of PVD, CVD and etch equipment for the semiconductor industry based in Newport, South Wales in the UK. We are a division of Orbotech, an Israeli maker of process and inspection equipment for the flat panel and PCB industries. SPTS are in the process of taking traditional Orbotech products (inkjet/3D printing and UV laser solutions) and introducing them to packaging applications. We have approximately 500 employees working worldwide.

Our product range includes:

Dielectric CVD: Our Delta® cluster systems grow SiO, SiN and SiON films primarily for the packaging, MEMS, RF and LED markets. We specialize in depositing PECVD films with low leakage, high breakdown strength at wafer temperatures of well less than 200 °C.

Plasma etch: Our Omega® and Mosaic® cluster systems serve the advanced packaging, MEMS, RF and LED markets. We are the market leaders for MEMS Si etching, and have extended that expertise to through Si vias (TSV), via reveal, Si thinning and more recently, plasma dicing.

Release etch: Our Primaxx™ systems are the MEMS market leaders in HF vapor phase removal of sacrificial silicon oxide, used to release silicon microstructures. Also for MEMS manufacturers, our Xactix™ systems use xenon difluoride to isotropically etch silicon.

Molecular Vapour Deposition (MVD®): MVD® deposits very thin, dense layers for uses such as wetting control in micro-fluidics (lab-on-a-chip, microplates), passivation on implantable devices, biocompatible surface coatings, and devices requiring functionalized surface coatings. 
Inkjet/3D printing: Orbotech’s digital additive printing solutions print UV curable acrylic materials, enabling solutions for a variety of applications. The systems can print on EMS, metals, PI, PBO, IC substrates and solder resist.

Via formation by laser: Orbotech’s Emerald™ series laser via formation system cuts <30µm holes through polyimide lined vias in TSV wafer level packaging. It simultaneously drills up to eight areas through patented Multi-Path Technology™.

PVD: Our Sigma® cluster systems are used in a variety of applications in power, RF, MEMS and advanced packaging markets. Applications include:
• Wafer front and backside metallization for power semiconductors. 
• AlN and ScAlN piezoelectric layers for filters and next generation MEMS 
• Front and backside metals for GaAs 
• Barrier and seed layers for TSVs in 2.5 and 3D packaging using long throw PVD for modest aspect ratios, and ionized PVD for the deepest vias.
• Under bump metallization (UBM) and redistribution layers (RDL) for advanced packaging. Our Sigma systems are used by all of the top 5 OSATs for wafer level packaging, and a number of leading foundries and IDMs. For fan-out wafer interconnect processing, we are the market leaders


YD: What are the specific needs of Fan-Out packaging for equipment manufacturers? In PVD?

DB:  The specific needs are no different from any wafer level packaging application; packaging companies using fan-out need low cost of ownership and high yield.  The challenge for us is to continue to offer high quality films at low cost as materials and steps change.  Fan-out (FO) processing presents a number of challenges to the equipment maker.  In contrast to most other applications we undertake, the actual metal deposition is straightforward.  The tricky part of fan-out wafer level packaging (FOWLP) processing is the wafer itself, and the process steps you perform to ready it for successful metallization.

YD: Which technology trends do you see in PVD? We see different solutions in how to deal with degas, temperature and contamination. How does SPTS position themselves in that context?

DB: FOWLP is still a relatively new technology, and the main focus at the fabs today is to expand the available market, meaning to drive cost-down to the point that the performance/cost trade-off is in a reasonable range of fan-in packaging. Thinner substrates, new materials don’t change the nature of the challenge for the PVD supplier, but they certainly don’t make it any easier. However, the selling arguments that took us to the #1 position in fan-out PVD are still very relevant:

• Multi-wafer degas in high vacuum. A fan-out wafer is a reconstituted substrate; the die are embedded within a wafer shaped epoxy-mold substrate. This epoxy, and the spin-on dielectrics applied later, contain a lot of moisture and other contaminants which must be removed before any metal is deposited, otherwise the RDL to pad contact will be compromised. Degassing wafers is a normal part of any PVD process: all PVD systems carry simple degas modules, relying on time and temperature to drive out moisture. But FO wafers have one particular twist – they do not tolerate high temperatures. The maximum temperature you can apply to a FO wafer is not much more than 130 °C. In a single wafer degas module at that temperature, you would need upwards of 30 minutes to adequately degas that wafer and that’s far too slow. So we developed a multi-wafer degas module, MWD, that carries up to 75 wafers vertically stacked in a high vacuum oven. A single wafer can spend 30 to 40 minutes being degassed, but because all wafers are processed in parallel, there is a “dry” wafer ready to process every 60 to 90 seconds.
The MWD is connected to the high vacuum side of the system, and that’s important. Pressure analysis of wafers degassed in vacuum and atmosphere show that when wafers are degassed on the atmospheric side, the vacuum recovery is slower and partial pressure of contaminating gases are higher.

• We use ICP (Inductively Coupled Plasma) technology for pre-clean. The pre-clean is probably the most critical step in the PVD process, where you clean the bond-pads with an Ar plasma. The goal is to create an atomically clean metal surface, to ensure a good metal to metal connection at the final deposition steps.
A pre-clean step is very normal for the vast majority of PVD processes, but you need to take more care with fan-out. The challenge is the organic based spin-on dielectric the packagers deposit on the top of the substrate. During the etch process, the “skin” on the dielectric is opened and it releases carbon monoxide. The CO will contaminate the bond pad, unless it is managed in the process – and that’s why we use ICP technology. In an ICP chamber, the plasma is created with one source, and a low bias is applied to the wafer to attract the etching ions. Other sputter systems use a capacitively coupled reactor (CCP) for pre-cleaning, where the wafer electrode creates the plasma and attracts the etching ions. Bias on the wafer is around 10 x higher than in our ICP. As shown in figure 1, the amount of CO released by the wafer increases with bias voltage. In the SE-LTX module, our ICP approach is less contaminating.

Yole FO wafers sigma preclean module spts
Figure 1:  FO wafers in the Sigma® preclean module release less CO than in CCP
(Source: SPTS Technologies)

• In-situ pasting in our SE-LTX module is more productive. Pasting inside the preclean module is a true back-end process, it is never seen in front-end fabs. Pasting refers to the practice of depositing material onto the chamber furniture, to “glue” potentially particle shedding layers. It’s needed because back-end fabs use organic dielectrics, and over time, carbon rich deposits will build up on furniture inside the preclean module and will start to flake. Without regular pasting, the chamber will need a PM after much less than 1,000 wafers. Pasting also helps keep the background levels of contaminating carbon monoxide (CO) low. All PVD systems in advanced WLP lines use pasting in their preclean modules, however they do not paste in the same way.

Our main competitors use pasting wafers. These are a wafer shaped substrate (eg silicon, ceramic, Ti), coated with a metal layer, usually Aluminum. A number of them are stored in the front of the PVD system and at regular intervals, one is handled into the preclean module and a short etch step is performed to deposit a thin layer of the pasting metal onto the chamber furniture. The substrate is then transported back to the storage unit. The secondary purpose of a paste is to keep the CO levels low, and to be effective, it has to be performed frequently. In practice, in high volume production, our competitors have to do a paste every 7 to 12 production wafers. That’s a heavy demand, and significantly reduces the theoretical production output.
Our SE-LTX module uses in-situ pasting – while the production wafer is etching, the chamber furniture is being pasted at the same time. That’s far more productive, and because it pastes every run, it is far more effective at keeping the CO levels low and that means Rc is lower and more repeatable. Depending on the nature of the polyimide coating, we might use a pasting wafer but very infrequently, perhaps at 800 to 1,000 wafer intervals.
In-situ pasting as employed in our SE-LTX preclean module is a more productive and efficient way of keeping particles in control, and Rc low and stable.


YD: Numerous types of Fan-Out packaging exist. How does SPTS handle this variety?

DB:  Fundamental differences at the wafer level like die face-up or face-down is of no consequence to the PVD step.  For the interconnect process, the challenge of different FO types comes down to amount of degassing and warpage, and we can manage that within the process window of our Sigma®.

YD: How do you see the Fan-Out packaging market growth in the future? How will it impact the equipment investment?

DB:  I am very optimistic for the FOWLP market.  We saw the first spike in fan-out production last year when TSMC went into volume.  I think this year will see only a modest increase in FO capacity, mainly because suppliers of traditional packages have cut costs to try and preserve their share.  However, I think from 2018 onwards, we will see another spike in FO adoption because costs will have dropped and performance risen.  The biggest growth will be in the high density sector, as other application processor companies move onto FO format.   I see the recent news of Qualcomm and Mediatek moving to TSMC for their 7nm production as a positive signal for the next phase of FO investments. Another interesting battle for share will be in high performance computing (HPC), where high density fan-out will start to overlap with 2.5D.  I expect for many applications, HDFO will win out.

YD: Panel for Fan-Out packaging is the new hot topic in the industry to reduce cost. Do you see a market appearing there? Does SPTS address that?

DB: SPTS does not address panel fan-out. We made the decision two years ago to focus on wafer level FO, and I still believe that was the right decision for us. Orbotech, our parent company, takes a different view and is very much engaged with the panel developers. Orbotech is a supplier of equipment to the flat panel and PCB markets, so panel format packaging is a natural home for them.
I can see a market for panel for low density FO applications; perhaps 10/10 um line/space at best with 1 RDL layer. Codec devices are one example that could be served by a panel FO provider.
High density FO, which will be the volume market in years to come will be made on wafers, not panel. I came to that conclusion some 3 years ago, and I have not changed my mind since. The challenges of high density packaging on panels are many; warpage, particles, shorts & open defects, multi interconnect levels. Further, the economics of panel FO is a tough sell too, because of the enormous capacity offered by a single line running 500x500mm panels. While I can see the first one into production having some success, I would be concerned that the second line will not find enough product to keep busy.
For an equipment vendor, making a brand new system for panel packaging is a risky venture. Aside from the fact that there is no standard substrate size, if you assume a reasonable adoption of panel format FO, then there would be only a handful of production equipment needed to satisfy the world’s demand. Very tough for an equipment make to make money at those sort of selling figures.

YD: What can we expect over the next 3 years from SPTS ?

DB: In packaging, we will expand our market share position across our product lines, and will add to our product portfolio. I expect business to grow in all the segments we serve, including TSV, which will finally become significant as HPC applications emerge in the fields of AI and machine learning. Plasma dicing will become an established method of singulating die, and will be the best way of separating devices made on very thin silicon. We will also see significant adoption of plasma dicing into the non-Si space: GaAs, GaN, perhaps even InP. Demand for WLP on 200mm to grow, as costs drop to near parity with wire-bonding.

Outside of packaging, RF will surge again as 5G comes on line, meaning strong growth for GaAs PA suppliers and BAW/SAW filter manufacturers. After a soft 18 months or so, MEMS will get a new boost of life from sectors outside of phones; automotive, IoT, BioMEMS. Low voltage piezoMEMS will become important for microphone arrays in personal/intelligent assistants, and for wearables. Autonomous cars will need inertial sensors with even greater accuracy, putting new demands on plasma sources.

Power semiconductors will continue to grow quickly, driven by electric vehicles, energy saving initiatives at a national level, and renewables. I think more power manufacturers will move their designs to 300mm, a transition that plays to some of our core strengths.



David Butler crop

David Butler currently serves as Executive Vice President and General Manager at SPTS Technologies with overall responsibility of product management and marketing of SPTS’s portfolio of industry leading etch and deposition process solutions and executive relationships with SPTS’s customers. Previously, David served as VP of product and corporate marketing, overseeing all marketing efforts for SPTS’s full range of PVD, Etch, CVD, and thermal products. With more than two decades of experience in the semiconductor capital equipment and related industries, David first joined Electrotech in 1988 as a Senior Process Engineer, then moved to Product Marketing for Electrotech’s PVD products.  In 2004, he assumed the role of Director of Marketing for the PVD/Etch/CVD products at Trikon, becoming Vice President of Marketing for the three product lines at Aviza Technology following the merger of Aviza and Trikon.



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