Everspin’s Spin Transfer Torque MRAM with perpendicular magnetic tunnel junction.
Reverse costing with:
- Detailed photos
- Precise measurements
- Material analysis
- Manufacturing process flow
- Supply-chain evaluation
- Manufacturing cost analysis
- Estimated sales price
Table of Contents
- Executive Summary
- Reverse Costing Methodology
- Summary of the Physical Analysis
- Package views
- Package cross-section
- Package opening
- STT MRAM Die
- Die view and dimensions
- Die cross section
- Die delayering and main blocks
- Die process characteristic
- STT MRAM Memory Die Front-End Process
- Fabrication Unit
- Manufacturing Process Steps
- Final Test and Packaging Fabrication Unit
- Summary of the Main Parts
- Summary of the Cost Analysis
- Yield Explanations and Hypotheses
- STT MRAM Memory Die Probe Test and Dicing
- STT MRAM memory front-end cost
- STT MRAM memory probe test, thinning and dicing
- STT MRAM memory wafer cost
- STT MRAM memory die cost
- Packaging Cost
- Final STT MRAM Component Cost
Amongst multiple emerging non-volatile memory (NVM) technologies, spin transfer torque magneto resistive RAM (STT-MRAM) has shown significant potential and market growth driven by low latency storage applications. In 2018 the MRAM market recorded revenue of $44 million. It is estimated that the compound annual growth rate for the MRAM market will be 85% between 2018 and 2024.
Magnetoelectronic memories have been employed in numerous information devices because of their non-volatile characteristics, high speed and low power consumption. Their high endurance characteristics have made STT MRAM a good competitor in the memory industry. It promises to pick up significant market share in the next few years.
Everspin’s STT MRAM component has a compact structure integrating numerous layers that include ferromagnetic and antiferromagnetic material, forming a magnetic tunnel junction. Different resistive states created in the MRAM cell allow read and write functions. A dielectric layer is coupled between two magnetic materials. A complex fabrication method is used to deposit and pattern the thin layers that form the STT MRAM cell.
Everspin Technologies leads the STT-MRAM market. Its 256Mb STT MRAM memory uses a 40 nm lithographic technology node process. The memory is manufactured along with CMOS transistors.
System Plus Consulting presents a deep analysis of Everspin’s EMD3256M STT MRAM. The report includes an analysis of the package and the dies, the MRAM cell, focusing on the layered material that makes up the MRAM cell. It also features a cost analysis and price estimation of the component. This cost analysis integrates the manufacture of CMOS transistors and MRAM cells. The manufacturing process steps are detailed, as is the supply chain. The manufacturing cost results are used to determine the cost per Mb for Everspin’s STT MRAM.
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