Table of contents 2

Scope of report 4

Executive summary 17

Context 66

• Semiconductor industry – players pursuing Moore’s law
• High-end performance packaging definition
• Scope of report
• High-end performance packaging market segment
• High-end performance packaging introduction

Market forecasts 75

• Market revenue
  • Total market revenue
  • Split by end-market
  • Split by technology
• Market units
  • Total market units
  • Split by end-market
  • Split by technology
• Package ASP split by technology
• Market value split by technology
  • 3D SoC
  • 3D stacked memory
  • 2.5D interposers
  • UHD FO
  • Embedded Si bridge
• Chapter conclusion

Market trends 96

• Cloud and edge computing
• Cloud computing and networking
• High-Performance Computing (HPC)
• Artificial intelligence for autonomous vehicles
• Chapter conclusion

Commercialized products and its supply chains 127

• Product launches
  • 3D stacked memories
  • (x)PU
  • GPU for HPC
• Supply chain for high-end performance packaging
  • Global mapping of high-end packaging
  • Global mapping based on technology
  • Supply chain for high-end packaging products
• Latest progress of key players
• Supply chain analysis in high-end performance packaging
  • Packaging supply chain analysis
• Analyst’s point of view on supply chain
  • It is a new battlefield for technology supremacy
  • Impact within big players
  • Impact on OSATs & substrate suppliers
  • What is TSMC strategy exactly ?
  • Who are the winners/losers?
• Chapter conclusion

IP Analysis: 3D SoC – Hybrid bonding 203

• Patent overview
• Supply chain IP position with examples
• Chapter conclusion

Technology trends 214

• Technology roadmap
  • Semiconductor packaging roadmap
  • Advanced packaging roadmap
  • High-end packaging roadmap: IO pitch vs IO density
  • High-end packaging roadmap: application technology
• Key players’ technology roadmap
• Short description of chiplets
• 3D SoC
• Hybrid bonding
  • Key players’ technologies: hybrid bonding for 3D SoC
• Commercial products available and future product launches
• TSV process
• 3D stacked memory
  • HBM
  • 3D stacking (3DS) DRAM
  • 3D SRAM
  • 3D NAND
  • Others: HMC, DRAM stacked memory
• 2.5D interposer
• Ultra-High-Density Fan-Out (UHD FO)
• Embedded Si bridge
• Other high-end packaging technologies
• Chapter conclusion

Report conclusion 318

Appendix 320

• OSAT high-end packaging technologies

Yole Corporate presentation 330

WHY IS HIGH-END PERFORMANCE PACKAGING’S ROLE INEVITABLY CRUCIAL TO THE SEMICONDUCTOR INDUSTRY?

Although Moore’s Law has remained alive for over five decades, it is no longer cost-efficient. When it comes to advanced lithographic nodes, lesser manufacturers can keep up. Now there are only three leading-edge players, Intel, Samsung and TSMC. The industry is now diligently using advanced packaging technologies to put multiple advanced and/or mature chips in a single package, which is also known as heterogeneous integration. Together with 2.5D/3D packaging this extends Moore’s Law at system-level.

Times have changed. The industry is seeking alternatives to design and manufacture the latest Systems on Chips (SoCs) using System in Package (SiP) and chiplet-based approaches by leveraging High-End Packaging to mix both the latest and mature nodes. 2.5D/3D packaging is accelerating into new technical breakthroughs for 3D Interconnect Density (3D ID). Such is the crucial role of high-end performance packaging in the semiconductor industry.

Prior to 2019, there has been very good tractions for High-End Packaging being commercialized in 3D stacked Dynamic Random Access Memory (DRAM), High Bandwidth Memory (HBM), Field-Programmable Gate Arrays (FPGA). It has been used in various processors including Central Processing Units (CPUs) and Graphics Processing Units (GPUs), in applications like processor cores, Solid State Drives (SSDs), memory blocks and graphics. Moving forward, more complexity and synergy of packaging technologies are expected for High Performance Computing (HPC) applications. For example, TSMC and Intel are working on hybrid bonding to package de-partitioned SoCs with Front-End (FE) capabilities. Intel and TSMC are working on big-scale chips processing with high input/output (I/O) density for high-end performance applications.

MARKET FORECAST FOR HIGH-END PERFORMANCE PACKAGING

The high-end packaging market is valued at $0.8B in 2019. It’s projected to reach $4.7B by 2025, with a Compound Annual Growth Rate (CAGR) of 32% from 2019 to 2025. In terms of package units, high-end packaging is projected to have a 38% CAGR, increasing from 204.5M Units in 2019 to 1409.2M Units in 2025.

The biggest market for high-end performance packaging comes from the telecom and infrastructure end-market, accounting for more than 60% from 2019 to 2025. high-end packaging is expected to grow fastest in “the mobile and consumer” and “automotive and mobility sectors,” at 60% and 88% respectively.

Among prominent digital age demands, High-End Packaging drivers are coming from the increased implementation and interest of end-system units in cloud computing, networking, HPC and consumer devices, personal computing and gaming. These key trends are paving the way for high-end packaging market opportunities.

In addition, the growth in consumer digitization and increase in adoption of internet of things, mobile connection and smart objects are expected to present major opportunities for the expansion of high-end performance packaging at the device level. They all need fast, big memory that interacts quickly with processing units. For example, in advanced computing for gaming, Through Silicon Vias (TSVs) are deployed in 3D stacked DRAM and HBM. By equipping GPUs with high-speed memory, high-performance gaming can be achieved. Also, Apple has released its upgraded iMac pro that integrates the AMD Radeon GPU Vega 10 pro.

Although the market for high-end packaging in automotive and mobility is small, the growth rate is one of the highest. The strong growth of high-end packaging in this market is mainly attributed to the growing adoption of artificial intelligence and robotics in vehicles.

IMPACT OF BIG PLAYERS IN HIGH-END PERFORMANCE PACKAGING SUPPLY CHAIN

Wafer Level Packages (WLPs) are changing the standard Front-End (FE)/Back-End (BE) supply chain. A middle-zone between FE and BE, where bumping and packaging can be executed on the wafer-level, can be reached by Outsourced Semiconductor Assembly and Test companies (OSATs), WLP houses and Integrated Device Manufacturers (IDMs).

Big players like Intel, TSMC and Samsung have successfully tapped into the advanced packaging market’s growth. They have achieved faster time-to-market than OSATs for high-end performance packaging, at historically unprecedented scale. This strategy of big players poses a direct , formidable threat to OSATs.

Big players have both FE and BE capabilities. As a foundry, TSMC can be fundamentally focused on just FE and BE hence the new focus on 3D SoIC. So TSMC can make decisions quickly and follow through its strategy effectively. Intel has been actively promoting and commercializing its high-end packaging technologies like Foveros, EMIB and hybrid bonding for future roadmap. Intel’s Foveros is a direct challenge with TSMC’s CoWoS. Although Samsung is leading TSV for HBM, it is not actively promoting logic 2.5D interposers. Samsung and Intel need to ensure there is agreement from its design group all the way to system department. Any form of change is restricted by many locked-in legacies that slow down the progression for them to achieve a leading position in advanced packaging, which is typically viewed as risky and low priority.

Within High-End Packaging, OSATs’ business is being cannibalized by foundries and IDMs. Moving forward, the fabless model may become more attractive thanks to cutting-edge turnkey services, such as the latest silicon node manufacturing technology coupled with advanced packaging. Fabless companies and design houses are looking to optimized packages for value-for-money, especially for high-end applications. If big players can provide both quality and cost benefits, then OSATs may have to stay defensive in the existing packaging domain.

ADI, AMD , Amkor, Annapurna/Amazon, arm, ASE, Atmel, Broadcom/Avago, Broadpak, CEA-Leti, Cerebras, Cisco, Cray , Cypress, eSilicon, Facebook, Fraunhofer IZM, Freescale, Fujitsu, GlobalFoundries, Gloway, Google, Hitachi, HLMC, Huawei, Ibiden, IBM, IME, IMEC, Infineon Technologies Intel, JCET, Juniper Networks, Kyocera, Micron, Mitsubishi, Nhanced, Nvidia, ON Semiconductor, Oracle, Panasonic, PTI, Qualcomm, Rambus, Renesas, Rohm, Samsung, Sanyo, SEMCO, Sharp, Shinko, SK hynix, SMIC, Sony, SPIL, STMicroelectronics, Tesla, Tezzaron, Texas Instruments, Toshiba, TSMC, UMC, Xilinx, Xperi, YMTC, and more.