Analysis of the unique Cascode JFET technology from UnitedSiC through the comparison of five of its 650V devices.
REVERSE COSTING WITH:
- Detailed optical and SEM photos
- Precise measurements
- Material EDX analysis
- Supply chain evaluation
- Manufacturing cost analysis
- Estimated selling price
- Technology and cost comparisons between Cascode JFETs and with SiC MOSFET of similar electrical performances.
Table of Content
- Executive Summary, Reverse Costing Methodology
- SiC Power Device Market
- UnitedSiC Profile, Portfolio and Technology
- Summary of the Physical Analysis
- Package Analysis
- Package opening
- Package cross-section
- SiC JFET Die
- JFET die view and dimensions
- JFET die process and cross-section
- Si MOSFET Die
- MOSFET die view and dimensions
- MOSFET die process and cross-Section
- JFET Die Front-End Process and Fabrication Unit
- MOSFET Die Front-End Process and Fabrication Unit
- Final Test and Packaging Fabrication Unit
- Overview of the Cost Analysis, Yield Explanations and Hypotheses
- JFET Die
- JFET front-end cost
- JFET die probe test, thinning and dicing
- JFET wafer and die cost
- MOSFET die
- MOSFET front-end cost
- MOSFET die probe test, thinning and dicing
- MOSFET wafer and die cost
- Complete Device
- Packaging cost
- Final test cost
- Component cost
- Estimation of Selling Price
- Comparison Between the Different Devices
- Comparison with SiC MOSFET with Similar Electrical Performance
The silicon carbide (SiC) power market is taking off and its value will approach US$2 billion by 2024. The reason is that SiC-based device penetration is expanding in different applications. Taking advantage of this growing market, UnitedSiC,, announced a strategic investment and long-term supply agreement with Analog Devices, Inc. (ADI) in March 2019.
UnitedSiC offers a large portfolio of SiC devices, mainly with its unique cascode co-pack configuration.
In this design, a Silicon MOSFET is combined with a SiC JFET in one package.
UnitedSiC offers two types of cascodes: UJ3C for “ease of use” when upgrading from a silicon device and UF3C for high-performance designs with faster switching. Moreover it proposes the latest solution in die assembling; the silver sintering.
In this report, System Plus Consulting presents a deep technology analysis of the 650V cascode family: five components are analysed across the UJ3C and UF3C series, assembled in two different types of packages; whith and without silver sintering.
Detailed optical pictures, scanning electron microscope cross-section, and energy-dispersive X-ray analyses are included to reveal UnitedSiC’s technical choices at the microscopic level of the die designs.
This report provides a detailed manufacturing cost analysis of the JFET, the MOSFET and the package as well as the estimated selling price of each one of the five cascode components.
Finally, this report compares the technological, physical parameters as well as the production cost and price of the Cascode JFET family’s devices.
A technology and cost comparison with a SiC MOSFET, with similar electrical performance, is also included.
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