2.5D / 3D TSV & Wafer-Level Stacking: Technology & Market Updates 2019

Yole Développement

2.5D heterogeneous and 3D wafer-level stacking are reshaping the packaging landscape.

 

What’s new

  • Two main market segments:

– Highigh-end segment: highperformance computing, networking, gaming, and AR/VR/ MR

– Mid/low-end segment: CMOS Image Sensors (CIS), MEMS, and LED

  • Semiconductor market mutation and its impact on stacking technologies
  • Through silicon via’s (TSV) extensive usage in HPC and networking hardware
  • 3D System on Chip (SoC) technology to hit the market by 2019
  • Hybrid bonding/stacking technology: markets, applications, forecasts, and players
  • Stacking technologies forecast for the CIS market Technologies that are challenging 2.5D TSV interposer

 

Key features of the report

  • Markets and applications requiring 3D stacking technologies
  • High-end market segment: stacking technologies (TSV, 2.5D interposer, and 3D SoC), supply chain and forecasts for HPC, networking, gaming, and AR/ VR/MR. Breakdown by product (stacked memory) and technology (2.5D and 3D SoC)
  • Mid/low-end segment: technologies (TSV and hybrid bonding), supply chain, and forecasts for CIS, MEMS, sensors, and LED. Breakdown by technology for CIS and LED, and by application for MEMS & sensors
  • The future of stacking technologies

Objectives of the report

  • Illustrate the impact of the semiconductor market’s mutation on packaging technologies
  • Outline three stacking technologies: through silicon via (TSV), 3D system-on-chip, and hybrid bonding
  • Provide an overview of the markets requiring stacking technologies, along with updated market data and forecasts
  • Describe the hardware and key applications that are/will use stacking technologies
  • Identify the main players and the supply chain for stacking technologies
  • Reference nascent solutions that may challenge some of the existing stacking technologies
  • Predict future applications where stacking technologies might be needed

 

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