Take a look at the fifth generation of EPC’s low voltage transistor
REVERSE COSTING WITH
- Detailed photos and identification
- Scanning electron microscope and energy-dispersive X-ray analysis of epitaxy layers and transistor structure
- Manufacturing process flow
- In-depth economic analysis
- Manufacturing cost breakdown
- Selling price estimation
- Comparison with Transphorm, GaNSystems, Texas Instruments and Panasonic devices
- Comparison with 100V silicon MOSFETs
Table of contents
Overview / Introduction
- Executive Summary
- Reserve Costing Methodology
- Summary of the Physical Analysis
- Package analysis
- Package opening
- Package cross-section
- FET Die
- FET die view and dimensions
- FET die process
- FET die cross-section
- FET die process characteristic
- Transistor Manufacturing Process
- FET die front-end process
- FET die fabrication unit
- Final test and packaging fabrication unit
- Summary of the Cost Analysis
- Yields Explanation and Hypotheses
- FET Die
- FET front-end cost
- FET die probe test, thinning and dicing
- FET wafer cost
- FET die cost
- Complete Device
- Packaging Cost
- Final test Cost
- Estimation of Selling Price
- Comparison of Epitaxy in GaN
- Comparison of Packaging of GaN Transistors
- Comparison Between 100V GaN-on-Silicon HEMT and Silicon MOSFETs
The low voltage GaN device market is increasingly important, and Efficient Power Conversion Corporation (EPC) is a major player in low voltage GaN-on-silicon high-electron-mobility transistor (HEMT) devices. 100V GaN HEMTs are a very new technology but they already compete with silicon transistors, especially in the field of megahertz high frequency applications.
System Plus Consulting has investigated the company’s EPC2045 device, its latest driving 100V for applications such as single-stage 48V converters, USB-C data and power connectors, LiDAR sensors, point-of-load converters and loads in open rack server architectures.
With its new transistor and GaN epitaxy design, the EPC2045 achieves a breakdown voltage of 100V for a current of 16A at 25°C, and a very low RdsOn on-resistance of 7mΩ compared to the previous generation.
The chip-scale packaging of EPC products reduces the final device cost and decreases its inductance, bringing advantages not only with respect to competitors in GaN, but also silicon.
Compared to silicon transistors, GaN process developments have significantly lowered capacitance. This translates into lower gate drive losses and lower device switching losses at higher frequencies for the same on-resistance and voltage rating.
Based on a complete teardown analysis, the report also provides an estimation of the production cost of the epitaxy and the package.
The report also compares the new product with previous EPC devices and epitaxy and GaNSystems, Transphorm, Panasonic and Texas Instruments packaging. This comparison highlights the differences in design and manufacturing processes and their impact on device size and production cost.
Related Reports & Monitors
Power SiC: MOSFETs, SBDs and Modules 2019 – Patent Landscape Analysis
Power GaN 2018: Epitaxy, Devices, Applications and Technology Trends
Market & Technology
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