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3DIC & 2.5D TSV Interconnect for Advanced Packaging 2014 Business Update
Oct.2014

2014-2019 tsv wafer star breakdown by application graph 2042399517
5 990 €

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Description

3DIC and 2.5D TSV Interconnect for Advanced Packaging Icone flyer3D TSV is in MEMS, CMOS Image Sensors and High-End Applications. When will it be used for mainstream consumer applications?


TSV IS A BUSINESS…LOOKING FOR WIDER ADOPTION!

Through Silicon Vias (TSV) technology was adopted in production a few years ago for MEMS and CMOS Image Sensors (CIS). Driven by consumer applications such as smartphones and tablets, this market is expected to continue to grow over the next several years. For high-end memories, 2015 will be the turning point for 3D adoption. Standards have now been established, therefore the industry will be ready to enter in high-volume manufacturing. Wide I/Os and logic-on-logic will follow, most probably around 2016-2017. Emerging applications, such as photonics based on interposer, are also being developed for future products. However, their market entrance is most likely not going to happen before 2019-2020. Figure1 illustrates the market adoption and growth for the next 5 years; additional information and details per application are available in the report (revenue, wspy, units 2013-2019, etc.).

 

2014-2019 TSV wafer star breakdown by application graph


MANY PLAYERS, DIFFERENT APPLICATIONS…HOWEVER, FUNDAMENTALLY ONLY TWO TSV MANUFACTURING OPTIONS

3D technology and specifically Through Silicon Via processing offer different options for processing wafers. As a result, different business models have been developed. Today, mainly two TSV approaches are being commonly used: via last and via middle. IDMs and wafer foundries are the main adopters of via middle manufacturing for memories and logic dies. They integrate interconnections between the front and back end of the line structures, offering a full device integration. Most of via middle activities are being done on 300mm wafers, and standard features for these TSVs are being established. In comparison, OSATs and Mid-End fabs, as well as MEMS foundries, are mostly focusing on via last integration approaches. OSATs are capable of performing wafer back side thinning, as well as via reveal processes, prior to bumping and stacking the dies. Figure 2 shows a map with key players coming from different business models using via middle integration. The report provides insights and detailed information on worldwide through-silicon-via activities for both via middle and via last, the companies involved, and comparison of their activities.

 

Landscape via Middle 3D


ONCE 3D IS ADOPTED IT WILL NEVER BE DROPPED…

What are the 3DIC market drivers today? Fundamentally, they have not changed over the years. Today, 3DIC is still driven by the need to increase performance and functionality, and to reduce form factor and cost. Adoption of 3DIC technology--due to its many advantages, as well as its ability to enable heterogeneous integration--is being considered for a wide range of applications. There is a significant advantage to using 3DIC; that is why this packaging platform is part of all the roadmaps of the key semiconductor players across the entire supply chain. Once 3D is adopted it will never be dropped! In the CMOS Image Sensor application the evolution of TSV has never stopped. Even though the integration methods used for CMOS Image Sensors have changed and evolved over the years (as shown in figure 3), TSV continued to be incorporated in the packaging of these devices, increasing functionality and enabling more efficient utilization of its silicon space. Sony, leader of the CMOS Image Sensor, by using a full-filled TSV and via last approach to stack the CIS onto a CMOS die, was able to more efficiently utilize (90%) its die surface area for the pixel array while decreasing the size of the die. This technology, called Exmor, is using a 3D stacked integration approach, and, currently is the new trend for this type of device as it enables a smaller die size and faster on-chip processing. The path is open for the heterogeneous integration of devices: MEMS are being integrated onto ASIC dies connected with TSVs (such as mCube, Bosch, with their accelerometer products, and others), and 3D stacked devices with integrated passives for medical applications, etc. The report provides technology roadmaps by device type and by main players.

 

CMOS Image Sensor evolution graph


NEXT MARKET ENTRY STRATEGY. WHAT COULD HAPPEN?

Driven by the need to further increase performance, 2015 will be the year for the implementation of 3D TSV technology in high-volume production. In the high-end market, volatile memory and especially DRAM motivates the needs of 3D adoption: Stacked memory dies can significantly lower power consumption and increase performance. Several announcements of new products using TSVs have been recently made. The key memory players have already started to ship samples this year and they are preparing to enter volume manufacturing towards the end of the year. SK Hynix plans to deliver this year High Bandwidth Memory (HBM) for graphic applications as a result of their collaboration work with AMD. Micron is shipping engineering samples of Hybrid Memory Cube (HMC) for high performance computing (HPC) and servers, and is reported to start volume production towards the end of 2014. Intel also recently revealed details of their new second generation Xenon Phi processor “Knights Landing” using a TSV based “on-package memory” solution developed in collaboration with Micron. Samsung has also shown progress in stacked DRAM: The 2nd generation Wide I/O approach was demonstrated using their “Widcon” technology and it is planned to be implemented in the next generation of Exynos processor for the consumer market.

3DIC will be adopted for high-end applications, no more doubts about that, since all key players have shown the technology on their roadmaps and real samples have already been shipped. The question about 3D adoption still remaining is: How and when will this really happen for the consumer market, where cost is so critical? Manufacturing costs require further reduction; equipment and materials suppliers, in collaboration with major players, are continuing their developments in this area to enable the industry to bring 3DIC on the consumer market.
Since node scaling is becoming more and more challenging and costly, 3D stacking using TSVs is definitely going to be (and already is) a viable option.



OBJECTIVES OF THE REPORT

  • Provide wafer forecast for the next five years and predict future application trends
  • Offer a commercialization status of current and future 3DIC products
  • Deliver an overview on key players and supply chain activities
  • What's new compared to last edition?
  • Overview of TSV implementation for various devices and packages (Memories, Logic, MEMS, Photonics, CMOS Image Sensors and other applications)
  • Market adoption roadmap
  • Wafer start by platform (3DIC, 2.5D)
  • Wafer start by application and market segment
  • Analysis of future 3D products for high-end applications
  • Alternative packaging technologies (fan out, advanced organic substrates, monolithic 3D) – Current status and future trends

Table of contents

Glossary
Motivations and objectives of the report
Who should be interested in this report?
Companies cited in this report
Executive summary
Introduction, definitions and report scope
Through Silicon Via
Major developments
TSV integration
Features landscape
Trends
Key Player and Supply Chain

Active players and geographic locations
Supply chain across different business models


Market Forecast
Market drivers
2013-2019 wafer start
2013-2019 breakdown by application
2013-2019 breakdown by units
2013-2019 revenues
3D TSVApplication Focus

Memories
Logic
CMOS Image Sensor
MEMS
Photonics
Others (LED, RF, Power…)
Alternative Packaging Technologies

Fan out technology
Advanced substrate
Monolithic 3D
Conclusions

Perspectives
Appendix

Recent key Press Headlines

 

Companies cited

Altera
AMD
Amkor
Apple
ASE
ASET
Avago Technologies
Broadcom
Teledyne DALSA
ITRI
eSilicon
Fraunhofer-IZM
Freescale
Fujitsu
Global Foundries
G-MEMS
Hua-Hong NEC
SK-Hynix
Ibiden
IBM
IMEC
IMT

Infineon
Intel
ITRI
JCAP
Leti
LSI Corporation
Marvell
mCube
Micron
Murata
Nanya
Nemotek
Renesas
Numonyx
nVidia
NXP
Oki Electric
Panasonic
Pico Computing
Qualcomm
Samsung
Silex Microsystems
Sematech
Shinko Electric
Sony
SPIL
StatsChipPAC
STEricsson
STMicroelectronics
SMIC
Tessera
Texas Instruments
TSMC
Tezzaron
Toshiba
TSMC
UMC
UTAC
Xintec
Xilinx
Ziptronix
ZyCube and much more…

 

KEY FEATURES OF THE REPORT

  • Through Silicon Vias (TSVs) integration characteristics & industry trends
  • Wafer start forecast 2013-2019 per application (MEMS, CIS, Memories…)
  • Wafer start forecast 2013-2019 per business models (OSATs, IDMs, Foundries, Mid End foundries…)
  • Detailed analysis of all TSV applications
  • Commercialization status per product family
  • Overview of TSV from different business models and wafer sizes
  • Technology roadmaps per product
  • Challenges still remaining to be addressed
  • Key industrial market player’s positioning: device makers, equipment & material suppliers, R&D centers, OSAT, foundries