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Epcos D7005 Closed-Loop Antenna Tuner
Feb.2013

img epcos emv1
3 290 €

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Description

Yole Epcos D7005 Closed-Loop Antenna Tuner iconeflyerThe first commercially available closed-loop antenna tuner
which supports all protocols (GSM, WCDMA/UMTS, LTE 700-2600MHz)
Extracted from the Japanese 4G version of the Samsung Galaxy S III

Epcos began development using RF MEMS technology, but switched to GaAs technology for their first antenna tuner.

With 4G being so widespread, the number of frequency bands needed becomes too large to be handled by discrete components. Tunable components are the solution and Epcos is the first to release a closed-loop antenna tuner which supports all protocols.

The D7005 antenna tuner is based on GaAs pHEMT technology, mixing Epcos and Sony devices.

It is a compact multi-chip module integrating a switchable high-Q capacitors die designed by Epcos and using Sony's JPHEMT and MIMC processes. The module also integrates a phase detector die designed by Epcos and manufactured with HBT transistors, a switch controller die and a 8-bit microcontroller.

The D7005 antenna tuner is targeted for mobile phones (especially 4G), tablets and data cards using single-feed antenna structures.

img epcos
This report provides a complete teardown of the antenna tuner with:

• Detailed photos
• Material analysis
• Manufacturing Process
• In-depth manufacturing cost analysis
• Supply chain evaluation
• Selling price estimation

Table of contents

Glossary
Overview/Introduction
TDK-EPC Company Profile
Samsung Galaxy S3 Teardown
Physical Analysis
> Physical Analysis Methodology
> Package Characteristics & Markings
> Package X-Ray
> Package Opening – Main Parts
> Package Cross-Section
> Capacitor Switch Die
- Die Dimensions & Markings
- Die Overview & Details
- Die Cross-Section (die thickness, metal layers, MIM capacitors, JPHEMT transistors)
- Process Characteristics & Wafer Fab
> Phase Detector Die
- Die Dimensions & Markings
- Die Delayering
- Die Cross-Section (die thickness, metal layers, MIM capacitors, deep trench isolation, HBT transistors)
- Process Characteristics & Wafer Fab

Physical Analysis (cont.)

> Switch Controller Die
- Die Dimensions & Markings
- Die Delayering
- Die Cross-Section (die thickness, metal layers)
- Process Characteristics & Wafer Fab
> MCU die
- Die Dimensions & Markings
- Die Delayering
- Die Cross-Section (die thickness, metal layers
- Process Characteristics & Wafer Fab

 Cost Analysis
> Synthesis of the Cost Analysis
>Yield Hypotheses
> Capacitor Switch Front-End Cost
> Capacitor Switch Die Cost
> Phase Detector Front-End Cost
> Phase Detector Die Cost
> Switch Controller Front-End Cost
> Switch Controller Die Cost
> MCU Front-End Cost
> MCU Die Cost
> Back-End: Packaging & Final Test Cost
> D7005 Component Cost (FE + BE)

Estimated Price Analysis

 



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