DescriptionAdopted for both mobile phone and consumer electronics applications, Fan-Out Wafer Level Packaging (FO-WLP) is the most innovative, advanced packaging technology today. Analysing patent status is the key to understanding the business situation.
ANALYSIS OF THE PATENT PORTFOLIO’S TECHNICAL CONTENT
After several years of specific analysis for customers, Yole Développement has decided to publish its first analysis concerning the technical contents of patents. This first study focuses on the FO-WLP area, a new packaging technology which is changing the patent landscape for semiconductor packaging across a wide range of application spaces. Yole Développement has developed a specific methodology to conduct this analysis (described below), mixing our technical and business knowledge with classical access to the patent database.A FEW COMPANIES WITH MANY PATENTS, MANY COMPANIES WITh A FEW PATENTS
A complex patent landscape: 10 companies dominate the FO-WLP IP space, but more than 120 organizations have patents in this field, representing 232 relevant patent families and 231 related patent families (in total, Yole Développement has identified more than 1,000 patents). This analysis provides an Excel file database of all relevant patents, enabling a multi-criteria search. The criteria are the same as those used for the technological segmentation:
- Patent information
- Patent publication number
- Priority date
- Patent family relationships
- FOWLP structure criteria
- FOWLP toolbox detail or improvement (die placement, bonding, encapsulation, carrier
- de-bonding, passivation, RDL, bumping,singulation)
- Additional elements to the original process
- Chip orientation
- Carrier shape
- Architecture details
- 2D structures
- 3D structures
- Stacked dies
- Use of vertical interconnects
- Technology used
- Packaged devices
It is also interesting to note the varying size of the players involved in this area.We find large companies like TSMC, as well as start-up /small players like Megica.The FO-WLP IP space was studied from several different angles, and our analysis provides information regarding patents filed by every kind of player, including the most recent assignees.
This complete description of the patent landscape is included in the first part of the analysis, and provides all the background materials for the FO-WLP patent landscape analysis.The analysis provides a complete summary of the patent landscape, including the patents’ geographic origins, company or R&D organizations that were granted the patents, historical data on when the companies applied for patents in the last 20 years, the patent inventor(s), expiration status, R&D collaborations,and more.
DETAILED ANALYSIS OF THE TOP10 FO-WLP PATENT ASSIGNEES
The analysis also offers an in-depth look at the patent portfolio of each of the TOP 10 patent assignees, including Infineon, ACE, Tessera, Samsung, Freescale, StatsChipPac, ASE, Amkor and STMicroelectronics.
For each of these companies, the analysis provides a comprehensive study of the patent portfolio, highlighting the following points:
- Company patent portfolio evolution
- Countries of deposition and patents’ origin
- Top inventors
- Process flow developed by the company (for commercially available devices)
- Technical segmentation of each patent portfolio
- Patent portfolio analysis for each manufacturing process step and architecture
- Main technical innovations
- Which patents are used in production today, and which patents exist to prepare the future generation of FO-WLP technologies (multi dies,panel scale FO-WLP, PoP FO-WLP, TMV, etc.)
- Remaining challenges for the company from Yole Développement’s perspective
In addition, the analysis highlights the strengths and weaknesses of each company’s patent portfolio and the developments currently implemented by each company.UNIQUE TECHNOLOGICAL ANALYSIS OF THE PATENT CONTENT AND IDENTIFICATION OF KEY PATENTS
Based on Yole Développement’s analysis of the technology trends in FO-WLP, the R&D of all worldwide players, and the teardown of the devices in production, we were able to identify and analyze the most important innovations for each process step of FO-WLP, from die placement and encapsulation to passivation and bumping. For each FO-WLP process step, the analysis provides the related patents and the evidence of its use in real devices, taking full benefit of the teardown analysis provided by our partner, System Plus Consulting.
For example, a strong focus is placed on Infineon’s eWLB technology, as well as on the 2nd generation FO-WLP patents describing new architectures using the eWLB solution (please see the full reverse analysis carried out by System Plus Consulting, titled “Infineon Fan-out WLP Reverse Costing Analysis”). As a synthesis, the analysis ranks the most important patents, highlights which of the analyzed documents are blocking, identifies which company owns such patents, and reviews the content of each patent. A UNIQUE METHODOLOGY OF ANALYSIS
Based on requests to Micropatent,Yole Développement has developed a unique methodology (described in the sample) for defining a technical segmentation of the patent landscape, and determining which patents are the most innovative, either for future implementation or for use in current production. By mixing its technical knowledge, business acumen and patent research, Yole Développement is able to provide unique evaluation and added value via this analysis.