The need for smaller packages, combined with ever-higher device performance and efficiency, drives the demand for thinned wafers and optimal surface roughness and chemistry.
The demand for thinned wafers (typically < 300 µm), therefore, has significantly increased over recent years and will continue to do so over the next five years with a forecast global CAGR of 5% over the 2019 – 2025 period. This will translate into a total equipment market revenue of $792 million in 2025 (Source: Thinning Equipment Technology and Market Trends for Semiconductor Devices report, Yole Développement, 2020).
Till now, from a substrate point of view, the semiconductor industry has traditionally been dominated by Si. However, new emerging applications with specific stringent requirements (size, performance, efficiency) are leading to the rise of alternative semiconductor substrate materials, such as GaAs, GaN, sapphire and SiC. Compared to Si, some of these materials are more challenging to process and require additional grinding/polishing steps. They also exhibit different chemistries. SiC is a very good example here. This material exhibits remarkable properties for power and RF electronics and is becoming more and more adopted by the industry. Power SiC device market, driven by the emerging electric vehicle applications, is expected to reach beyond US$2.6 billion by 2025. (Source: Compound Semiconductor Quarterly Market Monitor Q2-2020 Yole Développement, 2020). For precisely this reason, in parallel to its Si operation, Revasum is also focusing on SiC grinding, polishing, and cleaning solutions and has become the global leader in SiC thinning equipment solutions.
Yole Développement (Yole) recently met with Sarah Okada, VP of Marketing and Product Management at Revasum, to discuss today’s SiC ecosystem and Revasum’s latest equipment offerings as well as the company’s roadmap for the coming years.
This interview was conducted by Gaël Giusti, PhD., and Amandine Pizzagalli, MBA., Semiconductors & Manufacturing Market Analysts at Yole.
Gael Giusti (GG): Could you please introduce Revasum, its history and current activities?
Sarah Okada (SO): Revasum specializes in the design and manufacture of equipment used for the global semiconductor industry. Revasum’s equipment helps drive advanced manufacturing technology for critical growth markets, including automotive, IoT, and 5G. Our product portfolio includes state of the art equipment for the grinding, polishing, and CMP (Chemical Mechanical Planarization) processes used to manufacture devices for those key end markets. Revasum’s equipment is designed and developed in close collaboration with its customers.
Revasum was incorporated in 2016. The company headquarters are located San Luis Obispo, CA, USA.
GG: Revasum offers grinding and CMP tools for semiconductor devices. Could you please elaborate on Revasum’s core expertise, market focus and business model? What markets are you addressing? And which application(s) and market(s) mainly drive(s) Revasum’s revenue today?
SO: Revasum is an equipment manufacturer with core expertise in fully automated, single wafer, in-feed grinding and rotary polishing. We focus on semiconductor substrate and device markets. The main drivers in these markets are for Si prime wafer and SiC substrates for power and RF devices, which account for the bulk of our current revenue. These feed into the main end markets, which are automotive, IoT and 5G. The total revenue of the company is ~$12M per annum.
Amandine Pizzagalli (AP): Revasum is also focusing on SiC. Do you consider it as your main strength and is it a key element of differentiation in the wafer thinning industry?
SO: Yes, Revasum has majority market share for SiC grinding. The introduction of our new 6EZ SiC substrate polisher expands our capability to serve the SiC market. Another differentiator is our strong position in the Si prime wafer market. We are leveraging this knowledge for SiC substrate manufacturing.
GG: There are various thinning steps involved in the fabrication of semiconductor devices, like post slicing, planarization and thinning at the back-end level (wafer back-thinning). Can you describe Revasum’s involvement in the thinning process?
SO: Revasum’s grinding equipment is used on substrates to remove wire saw damage and to improve TTV post slicing or laser splitting. Grinding replaces lapping and diamond polish steps in a conventional batch process in substrate manufacturing. Another term for this process is pre-polish. In some cases, a short lapping step is still used prior to grinding. In this case, grinding still eliminates the need for a diamond polish step.
Revasum also offers polishing equipment for substrates to remove the grind damage and to smooth the surface of the wafer, preparing it for EPI deposition.
Note: Revasum’s grind to CMP process also eliminates multiple cleaning steps, each time the wafers are moved from one machine to the other.
During chip manufacture, Revasum’s CMP equipment is used to planarize thin films.
Once the devices have been built, Revasum’s grinders can be used for backside thinning or back grinding prior to packaging.
AP: Are technical specifications of the equipment different from one process step to another?
SO: Generally, a finer surface finish is required for substrate thinning than for backside thinning of device wafers. The grind wheels and recipes used for backside thinning vary from those used for substrate preparation. Substrates are freestanding and generally have a tighter TTV spec than for backside thinning of device wafers. The reason for this is twofold:
- TTV affects downstream processes, particularly deposition and lithography.
- Device wafers are typically mounted to a handle wafer using a temporary bond or back grinding tape to protect the front side and to support the device wafer during thinning.
The cumulative TTV of the stack limits the TTV improvement that can be achieved by the grind step.
GG: Are needs/specifications different from one semiconductor substrate to another? Do thinning requirements differ between SiC and Si-based substrates?
SO: Yes, Si substrate processing is much easier. The Si material is easier to work with and the manufacturing process is well understood and mature. The production scale is also very different between the two substrates. For example, a 150mm SiC boule yields only 20 wafers using conventional wire slicing methods, whereas an equivalent Si boule yields hundreds of wafers.
For this reason, reduction of kerf loss is a high priority for SiC substrate manufacturers. Wafers are sliced thinner to maximize yield from each boule. A full thickness, 150mm SiC substrate is about 350um thick, whereas a 150mm prime Si substrate is roughly 675um thick.
The consumables that work well for Si do not work at all for SiC, which is similar in hardness to diamond.
Wafer handling systems must also be modified for SiC due to the thickness variations and because the substrates are semi-transparent.
Another way that Si and SiC differ is in the behavior of the top and bottom faces of the wafer. The top and bottom of an Si wafer perform very similarly. Therefore double-side lapping and double-side polishing methods work. The top (Si face) and the bottom (C face) of an SiC wafer, however, perform differently under some conditions due to the atomic structure of the crystal. For example, the Si face is much more difficult to polish, so removal rates are slower than on the C face. For this reason, double-side processes (lapping, polishing) are not applicable to SiC manufacturing.
GG: What are the competitive advantages of your products?
SO: Revasum offers fully automated, single wafer process equipment that provides better wafer-to-wafer control and achieves higher productivity and yield than batch and manual equipment.
We are experts in both grind and CMP. For SiC substrate manufacturing, these process steps are interdependent. Optimized grinding results in shorter polishing steps, better TTV, reduced defects and lower production costs. Revasum’s grind and CMP solution eliminates the need for a diamond polish step as well as several cleaning steps, resulting in significant footprint savings and improved productivity.
Several key technologies offered by Revasum provide better process control enabling our customers to achieve tighter performance targets. Revasum’s SiC technologies and processes are easily scalable to 200mm.
AP: For which devices or substrate-based applications do you see a high interest for further thinning equipment and investment? And what are the main applications and thinning methods (Grinding vs. CMP) that will drive the next growth of the thinning equipment market?
SO: We see a high interest in equipment for power and RF devices for automotive, 5G and IoT. It is also important to take into account the transition to 150mm and 200mm SiC substrates.
Grinding and CMP or polish will both be required for substrate manufacturing.
In general, we see that SiC substrate manufacturers are looking for ways to improve productivity, reduce costs and improve wafer quality. This is part of what is driving the industry to transition to larger wafer sizes, but there is also a push to move away from manual, batch systems in favor of automated semiconductor-level equipment.
GG: Have we reached a saturation point/maturity in the wafer thinning equipment market or is there still room for innovation (clusters, new processes)? If yes, for which semiconductor devices?
SO: Indeed, there is still growth potential for thinning equipment in SiC. It is still a new market with room for innovation. As an example, we have recently seen the introduction of the laser split process as an alternative to wire slicing.
AP: How do you see the wafer thinning equipment market evolving in the years to come?
SO: At Revasum, we expect to see more wide-spread adoption of single wafer grinding and polishing equipment.
In parallel, the company expects to see improvements in the consumables (diamond grind wheels, slurry, and polishing pads, for example) in an effort to increase productivity and reduce manufacturing costs.
We also expect to see more end use applications for other devices based on wide bandgap semiconductor materials.
GG: Do you see the market becoming even more concentrated? Or are there still opportunities for new players to penetrate the thinning market?
SO: Revasum anticipates that there will be some consolidation, but there is also room for new players to enter the market. In fact, we see that new players are required to meet demand for sustained growth.
It is a bit of a chicken and egg problem. Device manufacturers understand the benefits of SiC and non-Si substrates, but they are hesitant to invest due to the fragile supply chain and high costs that plague the market today. Companies interested in breaking into the substrate manufacturing arena are nervous about demand.
What if there aren’t enough buyers for their substrates? Through innovation in technology and processes, we believe substrate and device makers alike will take the plunge. In fact, we are already seeing this happen.
AP: We have not yet discussed slurries, which is a much more fragmented market. Do you see this market becoming more concentrated and falling into the hands of equipment vendors or will it remain “independent”?
SO: Revasum does not sell slurries. However, we do provide our recommendations on all consumables required to achieve optimal performance on our equipment. Overall, there are only a handful of companies offering slurries for SiC. It not nearly as fragmented as the mainstream Semiconductor market.
According to Revasum, there will be more suppliers attempting to enter the market as the market grows.
However, this is such a specialized product that we don’t expect equipment vendors to take this on.
AP: And what is your analysis of the thinning equipment and material competitive landscape for semiconductor applications?
With the transition to 150mm and 200mm, single wafer processing equipment will win out over batch lapping and polishing. Disco remains a formidable competitor. The single wafer polishing landscape is much more open. Revasum is the first equipment supplier to offer a fully automated single wafer polisher designed specifically for SiC.
AP: As of today, the overall thinning equipment market is led by Japanese equipment vendors. Why do you think this is so? Is it only for historical reasons?
SO: While Disco (grind), Takitori (wire slicing) and Fujikoshi (300mm batch Si polish) have leading positions, there are other leading suppliers of lapping, polishing and CMP from outside of Japan, such as Gigamat (batch polish), PSS (Lapmaster, Peter Wolters) (batch lapping), Speedfam (batch polish) and Revasum (grind and polish).
GG: What is the status of Revasum in the thinning market and what changes do you expect in the future? According to you, what are the next steps and roadmap for Revasum?
SO: Revasum has majority market share in SiC thinning and in Si prime wafer polishing. The company expects to maintain its leadership position in these markets and also to gain #1 position in SiC substrate polishing.
The next step will be to establish our new single wafer polisher, the 6EZ for SiC substrate manufacturing. In addition, we would like to pursue new technology advancements to provide productivity and process improvements as well as reductions in manufacturing costs.
AP: Has your activity been impacted by the Covid-19 pandemic so far?
SO: Yes, in general COVID has slowed down capital expansion plans. Things are still moving forward, but all decisions have been pushed out.
Sarah Okada started in semiconductor industry in 1995 as a marketing assistant in the applications development group. During her career, she has been responsible for product management, market research, marketing communications, and new product development. In 2013, Ms. Okada was promoted to director of sales and marketing for Strasbaugh where she incorporated marketing and sales best practices to develop the new brand for Strasbaugh. Ms. Okada was key in the acquisition of Strasbaugh’s technology for Revasum in 2016. She has served as vice president of marketing and product management for the past 3 years, where she has been responsible for leading her team in the launch of the 6EZ, the World’s first fully automated, single wafer polisher designed specifically for SiC
Amandine Pizzagalli is a Technology & Market Analyst, Equipment & Materials – Semiconductor Manufacturing, at Yole Développement (Yole).
She is deeply involved in the development of the Semiconductor & Software division with the production of reports and custom consulting projects dedicated to the semiconductor equipment and materials industries and related manufacturing processes.
Amandine graduated from the engineering school, CPE Lyon (France), with a technical expertise in Semiconductor & Nano-Electronics and holds an electronics engineering degree followed by a master’s in semiconductor manufacturing technology from KTH Royal institute of technology (Sweden).
Gaël Giusti, PhD., is a Technology & Market Analyst specializing in Semiconductor Manufacturing and Equipment & Materials at Yole Développement (Yole). As part of the Semiconductor & Software division at Yole, Gaël’s expertise is focused on thin film growth and related applications, equipment, materials and manufacturing processes. He is involved daily in the production of technology & market reports and custom consulting projects.
Prior to Yole, Gaël served as a R&D engineer at Sil’Tronix Silicon Technologies for 5 years where he was in charge of upscaling a CVD process to develop epitaxial AlN thin film on sapphire for RF applications. He also worked on transparent conducting thin films for optoelectronics applications as a post-doctoral researcher at LMGP (Grenoble, France).
Gaël holds a master’s degree from ENSICAEN (Caen, France) as well as a PhD in Materials Science from the University of Birmingham (UK).
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