SPTS / Orbotech sponsors the Advanced Packaging and System Integration Symposium

Orbotech, with the acquisition of SPTS, now leads the equipment market for advanced packaging, advanced substrates and PCB, with deep roots throughout the electronic industry. Yole Développement has interviewed SPTS on its involvement in the Chinese market, its collaboration locally and also the evolution of its product strategy. SPTS has now been aggressively promoting its products and capabilities to the Chinese market for more than seven years.

The company has a solid installed base in multiple markets; MEMS in the first instance and now for RF and packaging.  And Chinese fabs want to reach beyond their domestic markets and use technology that enables them to compete on the highest level. Thanks to references from and experience working with world class customers, SPTS has been in a strong position from the outset. The following interview explores SPTS’ involvement in China in detail.

Yole Développement (YD): What are you expecting from this 2nd Advanced Packaging and System Integration Symposium co-organised by Yole and NCAP, and why did you decide to sponsor this event ?

David Butler (DB): I’m looking forward to meeting Chinese packaging experts and learning more about their ambitions and plans. My invited talk is a great opportunity to share our story with the wider community, and show NCAP and others how we can help them, as we have helped other packaging specialists such as STATS ChipPAC, Amkor, ASE, JCAP and Huatian. We sponsored this event because we want to build our brand in the biggest region for packaging equipment, and the goals of NCAP resonate with us. The Chinese government has set a target for domestic package suppliers to have world class technologies by 2020, and NCAP will play an important role in that initiative. We already supply solutions to three of their investors (JCAP, Huatian and China WLCSP) and are keen to expand those relationships.
Plus of course, we want to support Yole who have a good understanding of the advanced packaging market, and provide valuable analysis to us and others in the supply chain. Jerome Azemar, Technology and Market analyst at Yole Développement recently presented a well-received keynote for us at our annual technology seminar during SEMICON China on the FOWLP technologies and market trends.

YD: Could you please let us know more about the product portolio of SPTS?

DB: We sell 300mm bridge and <=200mm single wafer cluster systems. We serve a number of markets with our PVD, CVD, dry etch and vapor phase removal equipment, primarily in advanced packaging, MEMS, power semi and RF.
Unlike other equipment vendors, we also supply those different technologies on a single handling platform, providing huge flexibility and capability inside a single system. This represents excellent cost and space savings for customers at an early stage of development working within a constrained budget.

YD: How is SPTS as well as Orbotech positioned in the semiconductor area especially in the advanced packaging market?

DB: In advanced packaging, taking each product in turn.
Dry etch: Our Omega® fxP systems specialize in Si etching, taking our leading position in MEMS production into through silicon via (TSV) etch and high rate silicon thinning. For TSV, we have been in production for more than 10 years, used by early adopter via-last TSV exponents on CMOS image sensors and small form factor MEMS devices. If we include our MEMS business, we have >1,100 DRIE modules running the Bosch process, probably 10x more than the #2 vendor. We also offer complementary processes such as dielectric etching.
Our high rate blanket silicon etch activities are getting a lot of interest, first for via reveal and now for very thin wafer-to-wafer bonding, as announced by imec last July and in published papers. At >8 µm min-1, we etch blanket silicon 2 to 3x faster than any other dry etch vendor and are cost-competitive with wet etch processes but with a level of control that cannot be matched by chemical solutions.
A new and rapidly growing sub-market in packaging is plasma dicing, separating die by etching through the bulk of the Si wafer. Plasma dicing is a purely chemical process and so is far less damaging than mechanical saw or laser. It’s seen by many as a critical step in producing ultra-thin Si die. Mosaic™ fxP is the name for our plasma dicing system and our latest generation will process 300mm wafers on 400mm taped frames.

plasma diced bumped dieMosaic fxP
Plasma-diced bumped die (Courtesy of SPTS / Orbotech)Mosaic™ Rapier Plasma Dicing Module (Courtesy of SPTS / Orbotech)



PECVD: Our Delta® fxP systems deposits SiN, and both silane and TEOS based SiO at wafer temperatures <190°C. The ability to deposit stress engineered, electrically robust dielectrics at <190°C has many advantages in packaging, where we see increasing use of temperature sensitive materials:

  • In FOWLP, where the mold substrate has low tolerance to high temperatures and is usually accompanied by polymer based spin-on passivation layers, our low temperature dielectrics are used to oppose the tensile stress naturally imparted by spin-on layers, and thereby control warpage.
  • Via reveal passivation, deposited after the via tips have been exposed by a combination of grind plus dry etch. The thinned wafers are supported on a temporary carrier using a low temperature bond. Our low temperature dielectrics control warpage, and give excellent breakdown strength. 
  • For CMOS image sensors, we deposit low temperature dielectric liners into TSV, to provide electrical isolation and additional protection against diffusion. Our dielectrics are also used as a protective layer over polymer lenses, another temperature sensitive material.
  • We deposit TEOS oxides into via last TSV’s for small form factor devices such as MEMS, and some PMICS. These are typically thinned die supported on a temporary carrier, with a low temperature bonding layer. This market is growing, particularly for small gadget consumer markets.

PVD: Our Sigma® fxP is our biggest selling system into the packaging market. We deposit UBM and RDL for WLCSP applications, and for fan-out. We have ~75% share in the FOWLP market for PVD equipment, and are working with all the leading fan-out production companies. We have been successful in FO packaging for a number of reasons:

Sigma300 cropwarped wafer2
Sigma® fxP PVD system with MWD module (Courtesy of SPTS / Orbotech)Sigma PVD system handles wafer warpage up to 7mm (Courtesy of SPTS / Orbotech)

  • Solving contamination: All FO wafers feature singulated die embedded inside epoxy mold compound (EMC), with spin-on dielectrics surrounding the RDL. The EMC and dielectrics have a poor tolerance to high temperature and carry large amounts of contamination (moisture, CO) that must be removed before any metal deposition. Degassing wafers at low temperature takes a long time, and will drastically reduce the throughput of a sputter system. Our Sigma® fxP carries a multi wafer degas (MWD) module connected to the high vacuum side of the system, where up to 75 wafers are degassed at ~150°C in parallel before being passed into the processing chambers. Each one of those wafers may spend up to 30 minutes inside the MWD, but because they are processed in parallel, a “dry” wafer is available for metal deposition every 60 to 90 seconds.
  • Solving particles: The spin-on dielectrics used in packaging are almost always carbon based, such as polyimide or BCB. Before metal deposition, the wafers are always pre-cleaned in a sputter etch chamber, to remove trace oxide layers from the exposed metal contacts. At the same time, the dielectric will also be etched and carbon deposits will build up on surfaces inside the module. This carbon does not adhere well, and if not managed, will result in early particle failure, usually <1,000 wafers. In our SE-LTX pre-clean module, we have developed in-situ paste technology that effectively sticks the carbon deposition to the chamber surfaces at the same time as it is pre-cleaning the production wafers. Our customers are seeing class leading PM intervals >6,000 wafers. By doing in-situ pastes, we significantly reduce the frequency of dedicated wafer pastes, unlike other vendors who require production to be paused every 10 to 20 wafers to paste the chamber furniture. Our in-situ method means the system stays more productive.
  • Solving mis-handles: FO wafers are not as rigid as a full thickness Si wafers, and have a tendency to warp. The placement and shape of the embedded die will often increase the size of the bow. We have a lot of experience of handling problematic wafers from our work in the power semiconductor market, where IGBT wafers are thinned to <100um. We have taken that experience into the packaging industry with modified hardware, and control over-temperature rise & fall rates. Today, in routine FOWLP production, we are handling wafers with average bow of 3mm, and occasionally up to 7mm.
  • Highly productive: The combination of these features adds up to a PVD system with cost of ownership figures up to 50% less than competing tools. 

YD: With the competition between panel and wafer processing in some platforms how do you envision the future?

DB: With Yole, I wrote an article on FOWLP last year, where I said that panels would be used for low density packaging, much as it is now. 12 months later, I see no reason to change that position. Future FO will use wafers for high density (multi level wiring at <10 um L/S), and panels for low density (one or two level interconnect at >10um L/S). It is true that many IC makers and packagers look at panels as being the last word in low cost packaging. At a 30,000 feet level I get that argument, the lowest cost must come from running many die on a large area substrate. But the technical challenges are many:

  • Handling warpage over such a large area
  • Availability of hardware to print & pattern fine features
  • Cleanliness in the sub-micron particle size
  • Dealing with very low levels of contamination
  • Die shift
  • Thin film uniformities
  • No standards – what size panel to design for?
  • Multi-level wiring

The challenge is equipment availability. Re-purposing hardware once used for display panels appears to be a low cost route, but making those machines suitable for high density packaging is a huge task. High vacuum, sub-micron particle and cleanliness, removing low level gas contamination, multi-level wiring capability; none of this exists on panel sized equipment and I question the strength of motivation for equipment providers to develop it. Yole estimate the packaging revenues from panels will be ~$160M in 2020. Fabs usually spend ~10 to 15% of their income on equipment, putting the associated panel equipment capex at perhaps $20M. It’s a tough decision for any equipment maker to develop new systems for a TAM of just $20M. In contrast, the FO wafer market is perhaps 15x bigger and is an attractive proposition for equipment makers

The economics also need to be considered from the packager’s point of view. A panel line may cost $30M, in fact David Fang of PTI recently estimated the cost to be 30 to 40% greater than a FO wafer line. To make that line pay, it has to be filled. Based on Yole’s modest revenue estimates, it’s hard to see any packaging specialist getting enough business to fill the large capacity of a panel toolset. To make their lines more efficient, packagers like to re-purpose hardware as demand changes, for instance 12 to 8” wafer conversions in a traditional WLCSP line. A panel set-up is good for panels only, it could not take up wafer loading if panel demand dropped.

Panel equipment makers are faced with spending many millions of development dollars just to do what wafer based systems do now – with no technical benefit. Making a return on that investment looks tough. When panel hardware comes online, wafer based processing will have moved on. High density FO will not wait for panels to be ready.

YD: What do you think about the current supply chain ecosystem for advanced packaging?

DB: I am not best placed to discuss the rest of the supply chain, but my sense is that equipment is maturing and most of the issues have been sorted out. 3D memory is in production and high performance products on Si interposers are growing in number. FOWLP has been running since 2009, and those systems run at high volumes with >99% yield. 

YD: What will be your strategy to penetrate the Chinese market?

DB: We have been aggressively promoting our products and capabilities to the Chinese market for more than 7 years. We have a solid installed base in multiple markets; for MEMS in the first instance and now for RF and packaging. Chinese fabs want to serve not only their domestic markets, but also the markets overseas and want to use technology that enables them to compete on the highest level. Therefore, by showing strong references and experience learned in world class customers, we are immediately in a strong position. This is evidenced by business we recently won from two of China’s most ambitious packaging companies; JCAP and Huatian.
Chinese customers are keen to learn from the best vendors, so we spend a large part of our promotion and travel budgets on the Chinese market. This year we held our 7th technology seminar at SEMICON China, and attracted over 150 technologists from a variety of accounts – fabless, IDM’s, foundries and R&D institutions. They are very popular events with many questions and follow-on discussions with attendees.
We have also expanded our sales & support presence in the region, and have taken on new reps to cover the more remote parts of the country.

Sources :   www.yole.fr / www.spts.com

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