Targeting higher precision die attach – An interview with SET Corporation

Die attach is a key process step in semiconductor packaging. Today it is becoming more strategic, with lot of issues spanning devices across various applications, as a key contributor to assembly cost. Die attach equipment can be classified into two categories: die bonders and flip chip (FC) bonders. According to Yole Développement Die Attach Equipment Market 2019 report, the FC bonder market will grow with a 12% Compound Annual Growth Rate (CAGR) to reach US$290 million in 2024. By application, the fastest growth is in the stacked memory bonder market, with a 24% CAGR, followed by optoelectronics, with a 12% CAGR, and logic, with an 8% CAGR.

Die attach market share 2018 - 2024 forecast by application_Yole

There is consolidation going on in the assembly equipment business. Players are diversifying their tool offerings to support various business segments and assembly processes through mergers and acquisitions (M&As).

Pascal Metzger, General Manager of SET talked with Santosh Kumar, Principal Analyst & Director Packaging, Assembly & Substrates, Yole Korea. Read their exchange to understand what the stakes, issues and opportunities for SET in this challenging industry are.

Santosh Kumar: Could you please briefly introduce your company and its products and services?

Pascal Metzger: Founded in 1975, based in France, SET is a world leading supplier of high accuracy flip-chip bonders, both chip-to-chip and chip-to-wafer, and versatile nanoimprint lithography (NIL) solutions. With more than 350 pieces of equipment installed worldwide, SET is globally renowned for the unsurpassed accuracy and the flexibility of its flip-chip bonders. From manual loading to fully automated versions, the SET bonders adapt to all main bonding techniques.

SK: Die attach is a key process step in integrated circuit (IC) assembly and covers all devices across various applications. What are your focus markets in the die attach business?

PM: Etymologically, “die attach” means chip attachment. Our specialty is face-down flip-chip bonding, with full control of the bonding process. We also offer face-up and pick-and-place. SET does not offer wire bonding equipment.

SK: SET Corporation is one of the main players in the optoelectronics and silicon photonics assembly die attach equipment business. What are the key challenges in optoelectronics assembly from die attach perspectives? How do you address those challenges?

PM: Yes indeed, SET provides solutions very adapted to those markets, as soon as we talk about high assembly precision, below 1 µm.

This involves several challenges:

– the final precision that the customer needs

– the shape and the size of the components, and therefore their handling, for example, do not scratch the active face of a laser

– the alignment method: either on alignment marks, which is standard, or right on the geometry of the patterns, such as a laser ridge

To address such challenges, our equipment offer several features adapted to the client’s needs, to their applications, for example tools for handling and vision system for alignment.

SK: Assembly and packaging cost is still a significant portion of the total photonics device cost. What are the packaging trends in photonics devices, especially silicon photonics?  What are the main issues?

PM: Who says cost, says production. For production, you need high throughput. Moreover, as an equipment manufacturer, we have to respect the components, to guarantee high assembly efficiency and to offer the assembly processes requested by the customer.

We also pay attention to maintaining low cost of ownership, considering purchase cost, maintenance, operation, and a small footprint. Knowing that for a few years, packaging, previously the poor part of photonics, has become a field of prime importance. Indeed, nowadays we talk about “advanced packaging”.

SK: Wafer to wafer hybrid bonding is already implemented in some applications such as CMOS Image Sensor (CIS) wafer stacking. However, die to die (D2D) or die to wafer (D2W) hybrid bonding is still in the development phase, with many key players working on it. What is the status of D2D/D2W hybrid bonder equipment at SET Corporation? What are the main challenges you see from the equipment point of view? How can you solve it?

PM: The challenges of D2W hybrid bonding are the additional steps in the process, and therefore the cleaning/cleanliness of the chips, given their small footprint, preparation including Chemical Mechanical Preparation (CMP). Last year, SET launched NEO HB: the first flip-chip bonder in the world dedicated to hybrid bonding in D2W. This development was made within the scope of IRT Nanoelec, notably with the CEA-Leti teams in Grenoble, France.

NEO HB – Courtesy of SET

SK: What are the key packaging challenges for high power Radio Frequency (RF) devices for 5G applications?

PM: 5G requires very fast components, to be able to transmit huge quantities of data as video and pictures in a very short time. At the component level, it implies reducing the length of electrical connections, which implies small pitch between interconnections. At the assembly equipment level, it requires very high post-bond precision. Because 5G applies to large markets, it implies high throughput to be able to produce these RF components in large quantity. Today, there are equipment manufacturers offering very fast machines with modest precision. There are also extremely precise machines with very modest speed. The challenge is to be both fast and precise!

SK: What is the status of UV-NIL tool development at SET Corporation? You are collaborating with various industry partners on this technology. Can you briefly comment on this?

PM: Through the NaPa and NapaNIL European projects in the 2000s, SET developed know-how in step-and-repeat, as well as a dedicated machine: the NPS300, sold to many research centres. 

SK: The die attach business is dominated by few big players. How can SET Corporation maintain and enhance its position in the highly competitive market, especially when there is cost pressure from customers?

PM: SET is specialized in flip-chip bonders of very high precision – below micron levels. We do have a certain advantage in such precision levels, as we have already reached 0.3 µm post-bond accuracy in some applications. We are also the world leader in the assembly of large components, for example, image sensors and aerospace.

Furthermore, we do have a technological advance in hybrid bonding. As a leader in R&D machines, we know the needs of tomorrow’s market. In parallel, we offer production machines like NEO HB for hybrid bonding and ACCµRA Plus for thermocompression and reflow processes.

SK: There is consolidation going on in the assembly equipment business including die attach. Players are diversifying their tool offerings to support various business segments and assembly processes through mergers and acquisitions. Do you see this trend continuing in future? How will it affect your business?

PM: Trends come and go. SET is perfectly aware that the market changes very, very fast, even if it is limited by very high investment costs.  We watch this very carefully and we always adapt our equipment to the evolving needs of our clients.



More than 20 years ago, Pascal METZGER joined SET. He was initially in charge of mechanical and optical development projects and now he manages the company. SET is a world leader in high precision assembly equipment for semiconductor industry. Its culture is based on continuous innovation on technological solutions and solid team spirit among its employees.


Santosh Kumar

Santosh Kumar is currently working as Principal Analyst and Director Packaging, Assembly & Substrates, Yole Korea. Based in Seoul, Santosh is involved in the market, technology and strategic analysis of the microelectronic assembly and packaging technologies. His main interest areas are advanced IC packaging technology including equipment & materials. He is the author of several reports on fan-out / fan-in WLP, flip chip, and 3D/2.5D packaging. Santosh Kumar received the bachelor and master degree in engineering from the Indian Institute of Technology (IIT), Roorkee and University of Seoul respectively. He has published more than 40 papers in peer reviewed journals and has obtained 2 patents. He has presented and given talks at numerous conferences and technical symposiums related to advanced microelectronics packaging.


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